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* target/riscv: Implement second stage MMUAlistair Francis2020-02-272-19/+175
* target/riscv: Allow specifying MMU stageAlistair Francis2020-02-271-9/+28
* target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis2020-02-271-1/+15
* target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis2020-02-271-0/+13
* target/riscv: Disable guest FP support based on virtual statusAlistair Francis2020-02-271-0/+3
* target/riscv: Only set TB flags with FP status if enabledAlistair Francis2020-02-271-1/+4
* target/riscv: Remove the hret instructionAlistair Francis2020-02-272-6/+0Star
* target/riscv: Add hfence instructionsAlistair Francis2020-02-272-9/+54
* target/riscv: Add Hypervisor trap return supportAlistair Francis2020-02-271-10/+52
* target/riscv: Add hypvervisor trap supportAlistair Francis2020-02-271-10/+59
* target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis2020-02-271-2/+3
* target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis2020-02-271-0/+5
* target/riscv: Add support for virtual interrupt settingAlistair Francis2020-02-271-5/+28
* target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis2020-02-271-1/+12
* target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis2020-02-271-4/+20
* target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis2020-02-271-0/+3
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-273-0/+79
* target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis2020-02-271-0/+27
* target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis2020-02-271-0/+116
* target/riscv: Add Hypervisor CSR access functionsAlistair Francis2020-02-271-2/+134
* target/riscv: Dump Hypervisor registers if enabledAlistair Francis2020-02-271-0/+33
* target/riscv: Print priv and virt in disas logAlistair Francis2020-02-271-0/+8
* target/riscv: Fix CSR perm checking for HS modeAlistair Francis2020-02-271-4/+14
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-273-0/+26
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-273-0/+25
* target/riscv: Rename the H irqs to VS irqsAlistair Francis2020-02-272-9/+9
* target/riscv: Add support for the new execption numbersAlistair Francis2020-02-274-20/+37
* target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis2020-02-273-18/+48
* target/riscv: Add the Hypervisor extensionAlistair Francis2020-02-271-0/+1
* target/riscv: Convert MIP CSR to target_ulongAlistair Francis2020-02-272-2/+2
* target/riscv: progressively load the instruction during decodeAlex Bennée2020-02-252-23/+25
* Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEADPaolo Bonzini2020-02-257-19/+18Star
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| * Avoid cpu_physical_memory_rw() with a constant is_write argumentPhilippe Mathieu-Daudé2020-02-201-2/+2
| * Let cpu_[physical]_memory() calls pass a boolean 'is_write' argumentPhilippe Mathieu-Daudé2020-02-203-6/+6
| * Avoid address_space_rw() with a constant is_write argumentPeter Maydell2020-02-202-10/+9Star
| * Let address_space_rw() calls pass a boolean 'is_write' argumentPhilippe Mathieu-Daudé2020-02-202-5/+5
| * Remove unnecessary cast when using the cpu_[physical]_memory APIPhilippe Mathieu-Daudé2020-02-201-3/+3
| * Remove unnecessary cast when using the address_space APIPhilippe Mathieu-Daudé2020-02-204-4/+4
* | target/i386: check for empty register in FXAMPaolo Bonzini2020-02-251-1/+5
* | target/arm: Set MVFR0.FPSP for ARMv5 cpusRichard Henderson2020-02-211-4/+6
* | target/arm: Use isar_feature_aa32_simd_r32 more placesRichard Henderson2020-02-213-13/+11Star
* | target/arm: Rename isar_feature_aa32_simd_r32Richard Henderson2020-02-212-27/+28
* | target/arm: Convert PMULL.8 to gvecRichard Henderson2020-02-216-55/+95
* | target/arm: Convert PMULL.64 to gvecRichard Henderson2020-02-215-72/+39Star
* | target/arm: Convert PMUL.8 to gvecRichard Henderson2020-02-215-37/+39
* | target/arm: Vectorize USHL and SSHLRichard Henderson2020-02-216-66/+389
* | target/arm: Correctly implement ACTLR2, HACTLR2Peter Maydell2020-02-214-9/+33
* | target/arm: Use FIELD_EX32 for testing 32-bit fieldsPeter Maydell2020-02-211-9/+9
* | target/arm: Use isar_feature function for testing AA32HPD featurePeter Maydell2020-02-212-2/+7
* | target/arm: Test correct register in aa32_pan and aa32_ats1e1 checksPeter Maydell2020-02-216-79/+106
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