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* | target/arm: Correct handling of PMCR_EL0.LC bitPeter Maydell2020-02-211-4/+9
* | target/arm: Correct definition of PMCRDPPeter Maydell2020-02-211-1/+2
* | target/arm: Provide ARMv8.4-PMU in '-cpu max'Peter Maydell2020-02-211-0/+8
* | target/arm: Implement ARMv8.4-PMU extensionPeter Maydell2020-02-212-1/+39
* | target/arm: Implement ARMv8.1-PMU extensionPeter Maydell2020-02-211-2/+30
* | target/arm: Read debug-related ID registers from KVMPeter Maydell2020-02-213-0/+49
* | target/arm: Move DBGDIDR into ARMISARegistersPeter Maydell2020-02-215-12/+12
* | target/arm: Stop assuming DBGDIDR always existsPeter Maydell2020-02-214-19/+57
* | target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checksPeter Maydell2020-02-214-11/+25
* | target/arm: Define an aa32_pmu_8_1 isar feature test functionPeter Maydell2020-02-214-21/+27
* | target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON fieldPeter Maydell2020-02-211-1/+1
* | target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1Peter Maydell2020-02-213-4/+14
* | target/arm: Factor out PMU register definitionsPeter Maydell2020-02-211-76/+82
* | target/arm: Define and use any_predinv isar_feature testPeter Maydell2020-02-212-8/+6Star
* | target/arm: Add isar_feature_any_fp16 and document naming/usage conventionsPeter Maydell2020-02-212-2/+19
* | target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_panPeter Maydell2020-02-211-1/+1
* | target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registersPeter Maydell2020-02-215-10/+19
* | target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbidRichard Henderson2020-02-212-34/+37
* | target/arm: Remove ttbr1_valid check from get_phys_addr_lpaeRichard Henderson2020-02-211-5/+1Star
* | target/arm: Fix select for aa64_va_parameters_bothRichard Henderson2020-02-211-22/+24
* | target/arm: Use bit 55 explicitly for pauthRichard Henderson2020-02-211-1/+2
* | target/arm: Flush high bits of sve register after AdvSIMD INSRichard Henderson2020-02-211-0/+6
* | target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRNRichard Henderson2020-02-211-0/+1
* | target/arm: Flush high bits of sve register after AdvSIMD TBL/TBXRichard Henderson2020-02-211-0/+1
* | target/arm: Flush high bits of sve register after AdvSIMD EXTRichard Henderson2020-02-211-0/+1
* | target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definitionBALATON Zoltan2020-02-201-91/+54Star
* | target/ppc/cpu.h: Move fpu related members closer in cpu envBALATON Zoltan2020-02-201-5/+4Star
* | target/ppc: Fix typo in commentsBALATON Zoltan2020-02-202-5/+5
* | target/ppc/cpu.h: Remove duplicate includesBALATON Zoltan2020-02-201-2/+0Star
* | target/i386/whpx: Remove superfluous semicolonPhilippe Mathieu-Daudé2020-02-181-1/+1
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* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf2' i...Peter Maydell2020-02-141-9/+11
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| * riscv: Separate FPU register size from core register size in gdbstub [v2]Keith Packard2020-02-101-9/+11
* | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200213'...Peter Maydell2020-02-1411-118/+500
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| * | target/arm: Implement ARMv8.1-VMID16 extensionPeter Maydell2020-02-131-0/+1
| * | target/arm: Enable ARMv8.2-UAO in -cpu maxRichard Henderson2020-02-131-0/+4
| * | target/arm: Implement UAO semanticsRichard Henderson2020-02-131-20/+21
| * | target/arm: Update MSR access to UAORichard Henderson2020-02-134-0/+44
| * | target/arm: Add ID_AA64MMFR2_EL1Richard Henderson2020-02-133-2/+21
| * | target/arm: Enable ARMv8.2-ATS1E1 in -cpu maxRichard Henderson2020-02-132-0/+9
| * | target/arm: Implement ATS1E1 system registersRichard Henderson2020-02-131-6/+50
| * | target/arm: Set PAN bit as required on exception entryRichard Henderson2020-02-131-3/+50
| * | target/arm: Enforce PAN semantics in get_S1protRichard Henderson2020-02-132-0/+16
| * | target/arm: Update arm_mmu_idx_el for PANRichard Henderson2020-02-131-0/+9
| * | target/arm: Update MSR access for PANRichard Henderson2020-02-134-0/+43
| * | target/arm: Introduce aarch64_pstate_valid_maskRichard Henderson2020-02-132-0/+13
| * | target/arm: Remove CPSR_RESERVEDRichard Henderson2020-02-132-7/+8
| * | target/arm: Use aarch32_cpsr_valid_mask in helper_exception_returnRichard Henderson2020-02-131-2/+3
| * | target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_maskRichard Henderson2020-02-132-3/+4
| * | target/arm: Mask CPSR_J when Jazelle is not enabledRichard Henderson2020-02-131-1/+4
| * | target/arm: Split out aarch32_cpsr_valid_maskRichard Henderson2020-02-132-23/+38
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