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* Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into stagingRichard Henderson2021-11-024-2087/+845Star
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| * target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPUPhilippe Mathieu-Daudé2021-11-021-1/+0Star
| * target/mips: Fix Loongson-3A4000 MSAIR config registerPhilippe Mathieu-Daudé2021-11-021-0/+1
| * target/mips: Remove one MSA unnecessary decodetree overlap groupPhilippe Mathieu-Daudé2021-11-021-182/+180Star
| * target/mips: Remove generic MSA opcodePhilippe Mathieu-Daudé2021-11-022-9/+0Star
| * target/mips: Convert CTCMSA opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-58/+16Star
| * target/mips: Convert CFCMSA opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-9/+23
| * target/mips: Convert MSA MOVE.V opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-6/+20
| * target/mips: Convert MSA COPY_S and INSERT opcodes to decodetreePhilippe Mathieu-Daudé2021-11-022-88/+19Star
| * target/mips: Convert MSA COPY_U opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-26/+41
| * target/mips: Convert MSA ELM instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-13/+52
| * target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)Philippe Mathieu-Daudé2021-11-022-863/+106Star
| * target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)Philippe Mathieu-Daudé2021-11-022-34/+9Star
| * target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)Philippe Mathieu-Daudé2021-11-022-158/+35Star
| * target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)Philippe Mathieu-Daudé2021-11-022-12/+11Star
| * target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)Philippe Mathieu-Daudé2021-11-022-176/+76Star
| * target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)Philippe Mathieu-Daudé2021-11-022-39/+38Star
| * target/mips: Convert MSA VEC instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-75/+31Star
| * target/mips: Convert MSA 2R instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-75/+19Star
| * target/mips: Convert MSA FILL opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-12/+21
| * target/mips: Convert MSA 2RF instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-85/+53Star
| * target/mips: Convert MSA load/store instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-59/+36Star
| * target/mips: Convert MSA I8 instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-56/+27Star
| * target/mips: Convert MSA SHF opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-17/+22
| * target/mips: Convert MSA BIT instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-97/+101
| * target/mips: Convert MSA I5 instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-77/+41Star
| * target/mips: Convert MSA LDI opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-9/+21
| * target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_vPhilippe Mathieu-Daudé2021-11-022-18/+17Star
| * target/mips: Use enum definitions from CPUMIPSMSADataFormat enumPhilippe Mathieu-Daudé2021-11-021-3/+3
| * target/mips: Have check_msa_access() return a booleanPhilippe Mathieu-Daudé2021-11-021-7/+18
| * target/mips: Use dup_const() to simplifyPhilippe Mathieu-Daudé2021-11-021-20/+3Star
| * target/mips: Adjust style in msa_translate_init()Philippe Mathieu-Daudé2021-11-021-1/+3
| * target/mips: Fix MSA MSUBV.B opcodePhilippe Mathieu-Daudé2021-11-021-16/+16
| * target/mips: Fix MSA MADDV.B opcodePhilippe Mathieu-Daudé2021-11-021-16/+16
* | target/sparc: Set fault address in sparc_cpu_do_unaligned_accessRichard Henderson2021-11-022-13/+20
* | target/sparc: Split out build_sfsrRichard Henderson2021-11-021-26/+46
* | target/sparc: Remove DEBUG_UNALIGNEDRichard Henderson2021-11-021-9/+0Star
* | target/sh4: Set fault address in superh_cpu_do_unaligned_accessRichard Henderson2021-11-021-0/+5
* | target/s390x: Implement s390x_cpu_record_sigbusRichard Henderson2021-11-023-10/+26
* | target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemuRichard Henderson2021-11-022-10/+6Star
* | target/ppc: Set fault address in ppc_cpu_do_unaligned_accessRichard Henderson2021-11-021-0/+14
* | target/ppc: Move SPR_DSISR setting to powerpc_excpRichard Henderson2021-11-021-12/+9Star
* | target/microblaze: Do not set MO_ALIGN for user-onlyRichard Henderson2021-11-021-0/+16
* | target/arm: Implement arm_cpu_record_sigbusRichard Henderson2021-11-024-0/+10
* | target/alpha: Implement alpha_cpu_record_sigbusRichard Henderson2021-11-023-11/+28
* | target/xtensa: Make xtensa_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-023-23/+3Star
* | target/sparc: Make sparc_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-023-27/+2Star
* | target/sh4: Make sh4_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-023-12/+5Star
* | target/s390x: Implement s390_cpu_record_sigsegvRichard Henderson2021-11-023-12/+25
* | target/s390x: Use probe_access_flags in s390_probe_accessRichard Henderson2021-11-021-13/+5Star
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