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* target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson2019-03-151-14/+28
* target/arm: Check access permission to ADDVL/ADDPL/RDVLAmir Charif2019-03-151-8/+14
* target/arm: change arch timer registers access permissionDongjiu Geng2019-03-151-15/+15
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' i...Peter Maydell2019-03-1312-1589/+2891
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| * target/riscv: Remove decode_RV32_64G()Bastian Koppelmann2019-03-131-20/+1Star
| * target/riscv: Remove gen_system()Bastian Koppelmann2019-03-131-34/+0Star
| * target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-133-18/+18
| * target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2019-03-132-211/+164Star
| * target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-132-71/+81
| * target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-133-30/+34
| * target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-133-100/+108
| * target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2019-03-132-11/+24
| * target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2019-03-132-16/+25
| * target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2019-03-132-60/+33Star
| * target/riscv: Remove gen_jalr()Bastian Koppelmann2019-03-132-39/+27Star
| * target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann2019-03-133-81/+134
| * target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann2019-03-133-117/+195
| * target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann2019-03-134-38/+154
| * target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann2019-03-133-56/+126
| * target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann2019-03-133-600/+91Star
| * target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann2019-03-133-0/+389
| * target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann2019-03-132-0/+66
| * target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann2019-03-133-0/+415
| * target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann2019-03-133-144/+71Star
| * target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann2019-03-133-0/+178
| * target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann2019-03-134-9/+137
| * target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann2019-03-133-42/+88
| * target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann2019-03-133-12/+21
| * target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann2019-03-134-9/+206
| * target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann2019-03-134-10/+50
| * target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann2019-03-132-0/+58
| * target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann2019-03-133-11/+69
| * target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann2019-03-134-14/+92
* | target/hppa: exit TB if either Data or Instruction TLB changesSven Schnelle2019-03-121-4/+3Star
* | target/hppa: add TLB protection id checkSven Schnelle2019-03-126-9/+70
* | target/hppa: allow multiple itlbp without itlbaSven Schnelle2019-03-121-1/+1
* | target/hppa: fix b,gate instructionSven Schnelle2019-03-121-1/+12
* | target/hppa: ignore DIAG opcodeSven Schnelle2019-03-122-0/+10
* | target/hppa: remove PSW I/R/Q bit checkSven Schnelle2019-03-121-5/+0Star
* | target/hppa: add TLB trace eventsSven Schnelle2019-03-123-2/+39
* | target/hppa: report ITLB_EXCP_MISS for ITLB missesSven Schnelle2019-03-121-3/+1Star
* | target/hppa: fix TLB handling for page 0Sven Schnelle2019-03-121-5/+7
* | target/hppa: fix overwriting source reg in addbSven Schnelle2019-03-121-1/+3
* | target/hppa: Check for page crossings in use_goto_tbRichard Henderson2019-03-121-6/+4Star
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* spapr: Use CamelCase properlyDavid Gibson2019-03-121-2/+2
* target/ppc: Optimize x[sv]xsigdp using deposit_i64()Philippe Mathieu-Daudé2019-03-121-8/+4Star
* target/ppc: Optimize xviexpdp() using deposit_i64()Philippe Mathieu-Daudé2019-03-121-11/+3Star
* target/ppc: add HV support for POWER9Cédric Le Goater2019-03-121-1/+2
* target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and set_c...Mark Cave-Ayland2019-03-122-40/+14Star
* target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian...Mark Cave-Ayland2019-03-123-10/+10
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