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* target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson2019-03-151-14/+28
| | | | | | | | | | | Within a delay slot, we were squishing both DISAS_IAQ_N_STALE and DISAS_IAQ_N_STALE_EXIT to DISAS_IAQ_N_UPDATED. This lost the required exit to the main loop, and could result in interrupts never being delivered. Tested-by: Sven Schnelle <svens@stackframe.org> Reported-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Check access permission to ADDVL/ADDPL/RDVLAmir Charif2019-03-151-8/+14
| | | | | | | | | | | | These instructions do not trap when SVE is disabled in EL0, causing them to be executed with wrong size information. Signed-off-by: Amir Charif <amir.charif@cea.fr> Message-id: 1552579248-31025-1-git-send-email-amir.charif@cea.fr Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added 'target/arm' prefix to subject] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: change arch timer registers access permissionDongjiu Geng2019-03-151-15/+15
| | | | | | | | | | | | | | | | | | | Some generic arch timer registers are Config-RW in the EL0, which means the EL0 exception level can have write permission if it is appropriately configured. When VM access registers, QEMU firstly checks whether they have RW permission, then check whether it is appropriately configured. If they are defined to read only in EL0, even though they have been appropriately configured, they still do not have write permission. So need to add the write permission according to ARMV8 spec when define it. Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Message-id: 1552395177-12608-1-git-send-email-gengdongjiu@huawei.com Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' ↵Peter Maydell2019-03-1312-1589/+2891
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging target/riscv: Convert to decodetree Bastian: this patchset converts the RISC-V decoder to decodetree in four major steps: 1) Convert 32-bit instructions to decodetree [Patch 1-15]: Many of the gen_* functions are called by the decode functions for 16-bit and 32-bit functions. If we move translation code from the gen_* functions to the generated trans_* functions of decode-tree, we get a lot of duplication. Therefore, we mostly generate calls to the old gen_* function which are properly replaced after step 2). Each of the trans_ functions are grouped into files corresponding to their ISA extension, e.g. addi which is in RV32I is translated in the file 'trans_rvi.inc.c'. 2) Convert 16-bit instructions to decodetree [Patch 16-18]: All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus, we convert the arguments in the 16 bit trans_ function to the arguments of the corresponding 32 bit instruction and call the 32 bit trans_ function. 3) Remove old manual decoding in gen_* function [Patch 19-29]: this move all manual translation code into the trans_* instructions of decode tree, such that we can remove the old decode_* functions. Palmer: This, with some additional cleanup patches, passed Alistar's testing on rv32 and rv64 as well as my testing on rv64, so I think it's good to go. I've run my standard test against this exact tag. I still don't have a Mac to try this on, sorry! # gpg: Signature made Wed 13 Mar 2019 13:44:49 GMT # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.0-sf4: (29 commits) target/riscv: Remove decode_RV32_64G() target/riscv: Remove gen_system() target/riscv: Rename trans_arith to gen_arith target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Remove shift and slt insn manual decoding target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: Remove manual decoding from gen_store() target/riscv: Remove manual decoding from gen_load() target/riscv: Remove manual decoding from gen_branch() target/riscv: Remove gen_jalr() target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert RV priv insns to decodetree target/riscv: Convert RV64D insns to decodetree target/riscv: Convert RV32D insns to decodetree target/riscv: Convert RV64F insns to decodetree target/riscv: Convert RV32F insns to decodetree target/riscv: Convert RV64A insns to decodetree ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/riscv: Remove decode_RV32_64G()Bastian Koppelmann2019-03-131-20/+1Star
| | | | | | | | | | | | | | | | | | decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Remove gen_system()Bastian Koppelmann2019-03-131-34/+0Star
| | | | | | | | | | | | | | | | | | with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-133-18/+18
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| * target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2019-03-132-211/+164Star
| | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-132-71/+81
| | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-133-30/+34
| | | | | | | | | | | | | | | | | | | | | | manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-133-100/+108
| | | | | | | | | | | | | | | | | | | | gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2019-03-132-11/+24
| | | | | | | | | | | | | | | | | | With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2019-03-132-16/+25
| | | | | | | | | | | | | | | | | | With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2019-03-132-60/+33Star
| | | | | | | | | | | | | | | | | | We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Remove gen_jalr()Bastian Koppelmann2019-03-132-39/+27Star
| | | | | | | | | | | | | | | | | | trans_jalr() is the only caller, so move the code into trans_jalr(). Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann2019-03-133-81/+134
| | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann2019-03-133-117/+195
| | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann2019-03-134-38/+154
| | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann2019-03-133-56/+126
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann2019-03-133-600/+91Star
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann2019-03-133-0/+389
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann2019-03-132-0/+66
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann2019-03-133-0/+415
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann2019-03-133-144/+71Star
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann2019-03-133-0/+178
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann2019-03-134-9/+137
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann2019-03-133-42/+88
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann2019-03-133-12/+21
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann2019-03-134-9/+206
| | | | | | | | | | | | | | | | | | | | we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann2019-03-134-10/+50
| | | | | | | | | | | | | | | | | | | | | | this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann2019-03-132-0/+58
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann2019-03-133-11/+69
| | | | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
| * target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann2019-03-134-14/+92
| | | | | | | | | | | | | | | | | | | | for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
* | target/hppa: exit TB if either Data or Instruction TLB changesSven Schnelle2019-03-121-4/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code assumes that we don't need to exit the TB if a Data Cache Flush or Insert has happend. However, as we have a shared Data/Instruction TLB, a Data cache flush also flushes Instruction TLB entries, and a Data cache TLB insert might also evict a Instruction TLB entry. So exit the TB in all cases if Instruction translation is enabled. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-11-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: add TLB protection id checkSven Schnelle2019-03-126-9/+70
| | | | | | | | | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-10-svens@stackframe.org> [rth: Add required tlb flushing when prot id registers change.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: allow multiple itlbp without itlbaSven Schnelle2019-03-121-1/+1
| | | | | | | | | | | | | | | | | | The ODE software calls itlbp on existing TLB entries without calling itlba first, so this seems to be valid. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-9-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: fix b,gate instructionSven Schnelle2019-03-121-1/+12
| | | | | | | | | | | | | | | | | | | | | | b,gate does GR[t] ← cat(GR[t]{0..29},IAOQ_Front{30..31}); instead of saving the link address to register t. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-8-svens@stackframe.org> [rth: Move link check outside of ifndef CONFIG_USER_ONLY; use ctx->privilege; nullify the insn earlier.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: ignore DIAG opcodeSven Schnelle2019-03-122-0/+10
| | | | | | | | | | | | | | | | | | | | | | DIAG is usually only used by diagnostics software as it's CPU specific. In most of the cases it's better to ignore it and log a message that it's not implemented. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-7-svens@stackframe.org> [rth: Free the nullify condition.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: remove PSW I/R/Q bit checkSven Schnelle2019-03-121-5/+0Star
| | | | | | | | | | | | | | | | | | | | HP ODE use rfi to set the Q bit, and i don't see anything in the documentation that this is forbidden. So remove it. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-6-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: add TLB trace eventsSven Schnelle2019-03-123-2/+39
| | | | | | | | | | | | | | | | | | | | To ease TLB debugging add a few trace events, which are disabled by default so that there's no performance impact. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-5-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: report ITLB_EXCP_MISS for ITLB missesSven Schnelle2019-03-121-3/+1Star
| | | | | | | | | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-4-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: fix TLB handling for page 0Sven Schnelle2019-03-121-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assume the following sequence: pitlbe r0(sr0,r0) iitlba r4,(sr0,r0) ldil L%3000000,r5 iitlbp r5,(sr0,r0) This will purge the whole TLB and add an entry for page 0. However the current TLB implementation in helper_iitlba() will store to the last empty TLB entry, while helper_iitlbp() will write to the first empty entry. That is because an empty entry will match address 0 in helper_iitlba() Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-3-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: fix overwriting source reg in addbSven Schnelle2019-03-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | When one of the source registers is the same as the destination register, the source register gets overwritten with the destionation value before do_add_sv() is called, which leads to unexpection condition matches. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-2-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hppa: Check for page crossings in use_goto_tbRichard Henderson2019-03-121-6/+4Star
|/ | | | | | | | | | We got away with eliding this check when target/hppa was user-only, but missed adding this check when adding system support. Fixes an early crash in the HP-UX 11 installer. Reported-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* spapr: Use CamelCase properlyDavid Gibson2019-03-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The qemu coding standard is to use CamelCase for type and structure names, and the pseries code follows that... sort of. There are quite a lot of places where we bend the rules in order to preserve the capitalization of internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR". That was a bad idea - it frequently leads to names ending up with hard to read clusters of capital letters, and means they don't catch the eye as type identifiers, which is kind of the point of the CamelCase convention in the first place. In short, keeping type identifiers look like CamelCase is more important than preserving standard capitalization of internal "words". So, this patch renames a heap of spapr internal type names to a more standard CamelCase. In addition to case changes, we also make some other identifier renames: VIOsPAPR* -> SpaprVio* The reverse word ordering was only ever used to mitigate the capital cluster, so revert to the natural ordering. VIOsPAPRVTYDevice -> SpaprVioVty VIOsPAPRVLANDevice -> SpaprVioVlan Brevity, since the "Device" didn't add useful information sPAPRDRConnector -> SpaprDrc sPAPRDRConnectorClass -> SpaprDrcClass Brevity, and makes it clearer this is the same thing as a "DRC" mentioned in many other places in the code This is 100% a mechanical search-and-replace patch. It will, however, conflict with essentially any and all outstanding patches touching the spapr code. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Optimize x[sv]xsigdp using deposit_i64()Philippe Mathieu-Daudé2019-03-121-8/+4Star
| | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190309214255.9952-3-f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Optimize xviexpdp() using deposit_i64()Philippe Mathieu-Daudé2019-03-121-11/+3Star
| | | | | | | | The t0 tcg_temp register is now unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190309214255.9952-2-f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: add HV support for POWER9Cédric Le Goater2019-03-121-1/+2
| | | | | | | | | We now have enough support to boot a PowerNV machine with a POWER9 processor. Allow HV mode on POWER9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-16-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and ↵Mark Cave-Ayland2019-03-122-40/+14Star
| | | | | | | | | | | | | | | | | | | set_cpu_vsr{l,h}() Now that all VSX registers are stored in host endian order, there is no need to go via different accessors depending upon the register number. Instead we introduce vsr64_offset() and use it directly from within get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}(). This also allows us to rewrite avr64_offset() and fpr_offset() in terms of the new vsr64_offset() function to more clearly express the relationship between the VSX, FPR and VMX registers, and also remove vsrl_offset() which is no longer required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-8-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: switch fpr/vsrl registers so all VSX registers are in host ↵Mark Cave-Ayland2019-03-123-10/+10
| | | | | | | | | | | | | | | | | | | endian order When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) which are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also stored in host endian order to match the VMX registers. This ensures that TCG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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