| Commit message (Expand) | Author | Age | Files | Lines |
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| * | riscv: hmp: Add a command to show virtual memory mappings | Bin Meng | 2019-09-17 | 2 | -0/+233 |
| * | riscv: rv32: Root page table address can be larger than 32-bit | Bin Meng | 2019-09-17 | 1 | -5/+5 |
| * | target/riscv: Update the Hypervisor CSRs to v0.4 | Alistair Francis | 2019-09-17 | 1 | -17/+18 |
| * | target/riscv: Create function to test if FP is enabled | Alistair Francis | 2019-09-17 | 3 | -10/+26 |
| * | target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events | Philippe Mathieu-Daudé | 2019-09-17 | 2 | -21/+16 |
| * | target/riscv/pmp: Restrict priviledged PMP to system-mode emulation | Philippe Mathieu-Daudé | 2019-09-17 | 2 | -5/+2 |
| * | target/sparc: Switch to do_transaction_failed() hook | Peter Maydell | 2019-09-17 | 3 | -8/+18 |
| * | target/sparc: Remove unused ldl_phys from dump_mmu() | Peter Maydell | 2019-09-17 | 1 | -3/+1 |
| * | target/sparc: Handle bus errors in mmu_probe() | Peter Maydell | 2019-09-17 | 1 | -4/+25 |
| * | target/sparc: Correctly handle bus errors in page table walks | Peter Maydell | 2019-09-17 | 1 | -4/+20 |
| * | target/sparc: Check for transaction failures in MXCC stream ASI accesses | Peter Maydell | 2019-09-17 | 1 | -20/+37 |
| * | target/sparc: Check for transaction failures in MMU passthrough ASIs | Peter Maydell | 2019-09-17 | 1 | -16/+33 |
| * | target/sparc: Factor out the body of sparc_cpu_unassigned_access() | Peter Maydell | 2019-09-17 | 1 | -95/+106 |
| * | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell | 2019-09-17 | 1 | -1/+3 |
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| | * | hw/i386/pc: Extract e820 memory layout code | Philippe Mathieu-Daudé | 2019-09-16 | 1 | -0/+1 |
| | * | i386/kvm: support guest access CORE cstate | Wanpeng Li | 2019-09-16 | 1 | -1/+2 |
| * | | Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190915' into staging | Peter Maydell | 2019-09-16 | 1 | -5/+10 |
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| | * | target/hppa: prevent trashing of temporary in do_depw_sar() | Sven Schnelle | 2019-09-14 | 1 | -4/+6 |
| | * | target/hppa: prevent trashing of temporary in trans_mtctl() | Sven Schnelle | 2019-09-14 | 1 | -1/+4 |
| * | | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-sep-12-2019' ... | Peter Maydell | 2019-09-13 | 4 | -22/+15 |
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| | * | target/mips: gdbstub: Revert commit 8e0b373 | Libo Zhou | 2019-09-12 | 1 | -2/+1 |
| | * | target/mips: Switch to do_transaction_failed() hook | Peter Maydell | 2019-09-12 | 3 | -20/+14 |
| * | | target/xtensa: linux-user: add call0 ABI support | Max Filippov | 2019-09-11 | 2 | -4/+23 |
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| * | target/arm: Inline gen_bx_im into callers | Richard Henderson | 2019-09-05 | 1 | -19/+7 |
| * | target/arm: Clean up disas_thumb_insn | Richard Henderson | 2019-09-05 | 1 | -25/+2 |
| * | target/arm: Convert T16, long branches | Richard Henderson | 2019-09-05 | 2 | -49/+43 |
| * | target/arm: Convert T16, Unconditional branch | Richard Henderson | 2019-09-05 | 2 | -7/+8 |
| * | target/arm: Convert T16, load (literal) | Richard Henderson | 2019-09-05 | 2 | -40/+6 |
| * | target/arm: Convert T16, shift immediate | Richard Henderson | 2019-09-05 | 2 | -24/+10 |
| * | target/arm: Convert T16, Miscellaneous 16-bit instructions | Richard Henderson | 2019-09-05 | 2 | -87/+55 |
| * | target/arm: Convert T16, Conditional branches, Supervisor call | Richard Henderson | 2019-09-05 | 2 | -23/+15 |
| * | target/arm: Convert T16, push and pop | Richard Henderson | 2019-09-05 | 2 | -71/+22 |
| * | target/arm: Split gen_nop_hint | Richard Henderson | 2019-09-05 | 1 | -43/+24 |
| * | target/arm: Convert T16, nop hints | Richard Henderson | 2019-09-05 | 2 | -2/+18 |
| * | target/arm: Convert T16, Reverse bytes | Richard Henderson | 2019-09-05 | 2 | -15/+12 |
| * | target/arm: Convert T16, Change processor state | Richard Henderson | 2019-09-05 | 2 | -46/+50 |
| * | target/arm: Convert T16, extract | Richard Henderson | 2019-09-05 | 2 | -13/+11 |
| * | target/arm: Convert T16 adjust sp (immediate) | Richard Henderson | 2019-09-05 | 2 | -13/+11 |
| * | target/arm: Convert T16 add, compare, move (two high registers) | Richard Henderson | 2019-09-05 | 2 | -47/+12 |
| * | target/arm: Convert T16 branch and exchange | Richard Henderson | 2019-09-05 | 2 | -41/+39 |
| * | target/arm: Convert T16 one low register and immediate | Richard Henderson | 2019-09-05 | 2 | -42/+13 |
| * | target/arm: Convert T16 add/sub (3 low, 2 low and imm) | Richard Henderson | 2019-09-05 | 2 | -24/+18 |
| * | target/arm: Convert T16 load/store multiple | Richard Henderson | 2019-09-05 | 2 | -39/+17 |
| * | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson | 2019-09-05 | 2 | -11/+8 |
| * | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson | 2019-09-05 | 2 | -89/+38 |
| * | target/arm: Convert T16 load/store (register offset) | Richard Henderson | 2019-09-05 | 2 | -49/+17 |
| * | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson | 2019-09-05 | 2 | -145/+43 |
| * | target/arm: Add skeleton for T16 decodetree | Richard Henderson | 2019-09-05 | 3 | -0/+32 |
| * | target/arm: Simplify disas_arm_insn | Richard Henderson | 2019-09-05 | 1 | -53/+16 |
| * | target/arm: Simplify disas_thumb2_insn | Richard Henderson | 2019-09-05 | 1 | -76/+3 |
