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* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' in...Richard Henderson2021-10-291-1/+2
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| * target/i386: Remove core-capability in Snowridge CPU modelChenyi Qiang2021-10-291-1/+2
* | Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson2021-10-2912-57/+527
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| * target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao2021-10-291-4/+12
| * target/riscv: remove force HS exceptionJose Martins2021-10-293-33/+1Star
| * target/riscv: fix VS interrupts forwarding to HSJose Martins2021-10-291-20/+8Star
| * target/riscv: Allow experimental J-ext to be turned onAlexey Baturo2021-10-281-0/+4
| * target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev2021-10-283-2/+57
| * target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo2021-10-285-0/+17
| * target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo2021-10-281-0/+7
| * target/riscv: Add J extension state descriptionAlexey Baturo2021-10-281-0/+27
| * target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo2021-10-283-0/+298
| * target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo2021-10-281-0/+96
| * target/riscv: Add J-extension into RISC-VAlexey Baturo2021-10-281-0/+2
* | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211028' into stagingRichard Henderson2021-10-291-9/+14
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| * | host-utils: add 128-bit quotient support to divu128/divs128Luis Pires2021-10-281-4/+5
| * | host-utils: move checks out of divu128/divs128Luis Pires2021-10-281-5/+9
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* | Hexagon (target/hexagon) put writes to USR into temp until commitTaylor Simpson2021-10-294-2/+12
* | Hexagon (target/hexagon) more tcg_constant_*Taylor Simpson2021-10-294-21/+9Star
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* Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...Richard Henderson2021-10-231-5/+1Star
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| * disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé2021-10-221-5/+1Star
* | target/riscv: Compute mstatus.sd on demandRichard Henderson2021-10-223-20/+25
* | target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson2021-10-221-44/+45
* | target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson2021-10-223-52/+97
* | target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2021-10-222-17/+32
* | target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson2021-10-221-1/+6
* | target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2021-10-222-3/+39
* | target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-214-43/+62
* | target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson2021-10-211-14/+17
* | target/riscv: Properly check SEW in amo_opRichard Henderson2021-10-211-12/+14
* | target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson2021-10-211-1/+2
* | target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-215-1/+47
* | target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-216-32/+43
* | target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-216-67/+98
* | target/riscv: Create RISCVMXL enumerationRichard Henderson2021-10-211-3/+5
* | target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson2021-10-212-45/+48
* | target/riscv: Organise the CPU propertiesAlistair Francis2021-10-211-7/+10
* | target/riscv: Remove some unused macrosAlistair Francis2021-10-211-8/+0Star
* | target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang2021-10-212-8/+8
* | target/riscv: Fix orc.b implementationPhilipp Tomsich2021-10-211-5/+8
* | target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht2021-10-211-5/+5
* | target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang2021-10-211-1/+2
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* target/ppc: adding user read/write functions for PMCsDaniel Henrique Barboza2021-10-213-6/+80
* target/ppc: add user read/write functions for MMCR2Daniel Henrique Barboza2021-10-214-12/+99
* target/ppc: add user read/write functions for MMCR0Gustavo Romero2021-10-215-1/+128
* target/ppc: add MMCR0 PMCC bits to hflagsDaniel Henrique Barboza2021-10-213-0/+16
* target/ppc: Filter mtmsr[d] input before setting MSRMatheus Ferst2021-10-212-33/+41
* target/ppc: Fix XER access in monitorMatheus Ferst2021-10-211-1/+8
* linux-user: Fix XER access in ppc version of elf_core_copy_regsMatheus Ferst2021-10-212-2/+2
* target/ppc: Fix XER access in gdbstubMatheus Ferst2021-10-211-4/+4
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