summaryrefslogtreecommitdiffstats
path: root/target
Commit message (Expand)AuthorAgeFilesLines
* hvf: Simplify post reset/init/loadvm hooksAlexander Graf2021-06-031-1/+4
* hvf: Introduce hvf vcpu structAlexander Graf2021-06-038-234/+236
* hvf: Remove hvf-accel-ops.hAlexander Graf2021-06-031-2/+0Star
* hvf: Use cpu_synchronize_state()Alexander Graf2021-06-031-5/+4Star
* hvf: Split out common code on vcpu init and destroyAlexander Graf2021-06-031-21/+2Star
* hvf: Move hvf internal definitions into common headerAlexander Graf2021-06-031-30/+1Star
* hvf: Move cpu functions into common directoryAlexander Graf2021-06-033-306/+0Star
* hvf: Move vcpu thread functions into common directoryAlexander Graf2021-06-034-171/+1Star
* hvf: Move assert_hvf_ok() into common directoryAlexander Graf2021-06-031-32/+1Star
* target/arm: Enable BFloat16 extensionsRichard Henderson2021-06-033-0/+7
* target/arm: Implement bfloat widening fma (indexed)Richard Henderson2021-06-037-1/+82
* target/arm: Implement bfloat widening fma (vector)Richard Henderson2021-06-037-4/+73
* target/arm: Implement bfloat16 matrix multiply accumulateRichard Henderson2021-06-037-3/+81
* target/arm: Implement bfloat16 dot product (indexed)Richard Henderson2021-06-037-9/+80
* target/arm: Implement bfloat16 dot product (vector)Richard Henderson2021-06-037-0/+89
* target/arm: Implement vector float32 to bfloat16 conversionRichard Henderson2021-06-039-0/+95
* target/arm: Implement scalar float32 to bfloat16 conversionRichard Henderson2021-06-035-0/+51
* target/arm: Unify unallocated path in disas_fp_1srcRichard Henderson2021-06-031-9/+6Star
* target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16Richard Henderson2021-06-031-0/+15
* target/arm: use raise_exception_ra for stack limit exceptionJamie Iles2021-06-032-10/+4Star
* target/arm: use raise_exception_ra for MTE check failureJamie Iles2021-06-031-9/+3Star
* target/arm: fold do_raise_exception into raise_exceptionJamie Iles2021-06-031-10/+2Star
* target/arm: fix missing exception classJamie Iles2021-06-031-2/+9
* target/arm: Mark LDS{MIN,MAX} as signed operationsRichard Henderson2021-06-031-3/+10
* target/arm: Allow board models to specify initial NS VTORPeter Maydell2021-06-032-0/+12
* target/arm: Make FPSCR.LTPSIZE writable for MVEPeter Maydell2021-06-033-4/+9
* target/arm: Implement M-profile VPR registerPeter Maydell2021-06-033-0/+63
* target/arm: Fix return values in fp_sysreg_checks()Peter Maydell2021-06-031-3/+3
* target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dpPeter Maydell2021-06-031-2/+13
* target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dpPeter Maydell2021-06-031-18/+19
* target/arm: Update feature checks for insns which are "MVE or FP"Peter Maydell2021-06-031-19/+29
* target/arm: Add isar feature check functions for MVEPeter Maydell2021-06-031-0/+22
* target/ppc: fix single-step exception regressionLuis Pires2021-06-031-3/+2Star
* target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetreeMatheus Ferst2021-06-033-52/+45Star
* target/ppc: Move addpcis to decodetreeMatheus Ferst2021-06-033-9/+13
* target/ppc: Implement vcfuged instructionMatheus Ferst2021-06-033-0/+64
* target/ppc: Implement cfuged instructionMatheus Ferst2021-06-034-0/+79
* target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructionsMatheus Ferst2021-06-032-0/+33
* target/ppc: Implement prefixed integer store instructionsRichard Henderson2021-06-032-0/+16
* target/ppc: Move D/DS/X-form integer stores to decodetreeRichard Henderson2021-06-033-82/+49Star
* target/ppc: Implement prefixed integer load instructionsRichard Henderson2021-06-032-0/+31
* target/ppc: Move D/DS/X-form integer loads to decodetreeRichard Henderson2021-06-033-123/+150
* target/ppc: Implement PNOPRichard Henderson2021-06-032-0/+78
* target/ppc: Move ADDI, ADDIS to decodetree, implement PADDIRichard Henderson2021-06-034-29/+64
* target/ppc: Add infrastructure for prefixed insnsRichard Henderson2021-06-036-6/+95
* target/ppc: Move page crossing check to ppc_tr_translate_insnRichard Henderson2021-06-031-3/+6
* target/ppc: Introduce macros to check isa extensionsRichard Henderson2021-06-031-0/+26
* target/ppc: powerpc_excp: Consolidade TLB miss codeFabiano Rosas2021-06-031-35/+2Star
* target/ppc: powerpc_excp: Remove dump_syscall_vectoredFabiano Rosas2021-06-031-13/+1Star
* target/ppc: powerpc_excp: Move lpes code to where it is usedFabiano Rosas2021-06-031-22/+25