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* | target/arm: Detect overflow when calculating next PMU interruptPeter Maydell2022-09-141-8/+14
* | target/arm: Honour MDCR_EL2.HPMD in Secure EL2Peter Maydell2022-09-141-10/+7Star
* | target/arm: Ignore PMCR.D when PMCR.LC is setPeter Maydell2022-09-141-4/+13
* | target/arm: Don't mishandle count when enabling or disabling PMU countersPeter Maydell2022-09-141-0/+45
* | target/arm: Correct value returned by pmu_counter_mask()Peter Maydell2022-09-141-1/+1
* | target/arm: Don't corrupt high half of PMOVSR when cycle counter overflowsPeter Maydell2022-09-141-1/+1
* | target/arm: Add missing space in commentPeter Maydell2022-09-141-1/+1
* | target/arm: Advertise FEAT_ETS for '-cpu max'Peter Maydell2022-09-142-0/+5
* | target/arm: Implement ID_DFR1Peter Maydell2022-09-143-2/+5
* | target/arm: Implement ID_MMFR5Peter Maydell2022-09-143-2/+5
* | target/arm: Sort KVM reads of AArch32 ID registers into encoding orderPeter Maydell2022-09-141-2/+2
* | target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8Peter Maydell2022-09-141-5/+60
* | target/arm: Add cortex-a35Hao Wu2022-09-141-0/+80
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* target/riscv: Update the privilege field for sscofpmf CSRsAtish Patra2022-09-071-30/+60
* hw/riscv: virt: Add PMU DT node to the device treeAtish Patra2022-09-072-0/+58
* target/riscv: Add few cache related PMU eventsAtish Patra2022-09-071-0/+25
* target/riscv: Simplify counter predicate functionAtish Patra2022-09-071-101/+9Star
* target/riscv: Add sscofpmf extension supportAtish Patra2022-09-077-11/+623
* target/riscv: Add vstimecmp supportAtish Patra2022-09-076-6/+118
* target/riscv: Add stimecmp supportAtish Patra2022-09-078-1/+235
* hw/intc: Move mtimer/mtimecmp to aclintAtish Patra2022-09-072-5/+2Star
* target/riscv: Use official extension names for AIA CSRsAnup Patel2022-09-074-14/+26
* target/riscv: Add xicondops in ISA entryRahul Pathak2022-09-071-0/+1
* target/riscv: Remove additional priv version check for mcountinhibitAtish Patra2022-09-071-8/+0Star
* target/riscv: Fix priority of csr related check in riscv_csrrw_checkWeiwei Li2022-09-071-19/+25
* target/riscv: Add Zihintpause supportDao Lu2022-09-074-1/+25
* target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...eopXD2022-09-071-0/+1
* target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen2022-09-072-2/+25
* target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen2022-09-072-0/+14
* target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen2022-09-072-0/+38
* target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...Yueh-Ting (eop) Chen2022-09-071-10/+16
* target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen2022-09-072-0/+11
* target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen2022-09-072-0/+8
* target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen2022-09-072-0/+5
* target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen2022-09-072-11/+29
* target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen2022-09-076-2/+20
* target/riscv: Fix typo and restore Pointer Masking functionality for RISC-VAlexey Baturo2022-09-071-1/+1
* target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...Weiwei Li2022-09-071-13/+5Star
* target/riscv: Fix checks in hmode/hmode32Weiwei Li2022-09-072-7/+7
* target/riscv: Add check for csrs existed with U extensionWeiwei Li2022-09-071-3/+21
* target/riscv: Fix checkpatch warning may triggered in csr_ops tableWeiwei Li2022-09-071-207/+234
* target/riscv: H extension depends on I extensionWeiwei Li2022-09-071-0/+6
* target/riscv: Add check for supported privilege mode combinationsWeiwei Li2022-09-071-0/+6
* target/riscv: move zmmul out of the experimental propertiesWeiwei Li2022-09-071-1/+2
* target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot2022-09-072-5/+22
* target/riscv: Force disable extensions if priv spec version does not matchAnup Patel2022-09-071-56/+94
* target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel2022-09-073-6/+296
* target/riscv: Make translator stop before the end of a pageRichard Henderson2022-09-061-4/+13
* target/riscv: Add MAX_INSN_LEN and insn_lenRichard Henderson2022-09-061-1/+9
* target/i386: Make translator stop before the end of a pageIlya Leoshkevich2022-09-061-24/+38
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