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path: root/tcg/loongarch64/tcg-target.c.inc
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* tcg/loongarch64: Add direct jump supportQi Hu2022-10-251-4/+44
* tcg/loongarch64: Support raising sigbus for user-onlyWANG Xuerui2022-02-081-2/+69
* tcg/loongarch64: Fix fallout from recent MO_Q renamingWANG Xuerui2022-02-081-1/+1
* tcg/loongarch64: Register the JITWANG Xuerui2021-12-211-0/+44
* tcg/loongarch64: Implement tcg_target_initWANG Xuerui2021-12-211-0/+27
* tcg/loongarch64: Implement exit_tb/goto_tbWANG Xuerui2021-12-211-0/+19
* tcg/loongarch64: Implement tcg_target_qemu_prologueWANG Xuerui2021-12-211-0/+68
* tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st opsWANG Xuerui2021-12-211-0/+353
* tcg/loongarch64: Implement simple load/store opsWANG Xuerui2021-12-211-0/+131
* tcg/loongarch64: Implement tcg_out_callWANG Xuerui2021-12-211-0/+34
* tcg/loongarch64: Implement setcond opsWANG Xuerui2021-12-211-0/+69
* tcg/loongarch64: Implement br/brcond opsWANG Xuerui2021-12-211-0/+53
* tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu opsWANG Xuerui2021-12-211-0/+65
* tcg/loongarch64: Implement add/sub opsWANG Xuerui2021-12-211-0/+38
* tcg/loongarch64: Implement shl/shr/sar/rotl/rotr opsWANG Xuerui2021-12-211-0/+91
* tcg/loongarch64: Implement clz/ctz opsWANG Xuerui2021-12-211-0/+42
* tcg/loongarch64: Implement bswap{16,32,64} opsWANG Xuerui2021-12-211-0/+32
* tcg/loongarch64: Implement deposit/extract opsWANG Xuerui2021-12-211-0/+21
* tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc opsWANG Xuerui2021-12-211-0/+88
* tcg/loongarch64: Implement sign-/zero-extension opsWANG Xuerui2021-12-211-0/+82
* tcg/loongarch64: Implement goto_ptrWANG Xuerui2021-12-211-0/+15
* tcg/loongarch64: Implement tcg_out_mov and tcg_out_moviWANG Xuerui2021-12-211-0/+137
* tcg/loongarch64: Implement the memory barrier opWANG Xuerui2021-12-211-0/+32
* tcg/loongarch64: Implement necessary relocation operationsWANG Xuerui2021-12-211-0/+66
* tcg/loongarch64: Define the operand constraintsWANG Xuerui2021-12-211-0/+52
* tcg/loongarch64: Add register names, allocation order and input/output setsWANG Xuerui2021-12-211-0/+118
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