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* [ioapi] Allow iounmap() to be called for port I/O addressesMichael Brown2025-11-051-5/+10
* [riscv] Correct page table stride calculationMichael Brown2025-10-271-1/+1
* [riscv] Place explicitly zero-initialised variables in the .data sectionMichael Brown2025-07-301-0/+7
* [riscv] Allow for poisoning .bss section before early initialisationMichael Brown2025-07-301-0/+51
* [riscv] Ensure coherent DMA allocations do not cross cacheline boundariesMichael Brown2025-07-111-0/+15
* [riscv] Support the standard Svpbmt extension for page-based memory typesMichael Brown2025-07-111-0/+20
* [riscv] Create coherent DMA mapping of 32-bit address space on demandMichael Brown2025-07-114-70/+77
* [riscv] Use 1GB pages for I/O device mappingsMichael Brown2025-07-111-9/+9
* [riscv] Invalidate data cache on completed RX DMA buffersMichael Brown2025-07-102-16/+47
* [riscv] Add optimised TCP/IP checksummingMichael Brown2025-07-102-0/+153
* [riscv] Provide a DMA API implementation for RISC-V bare-metal systemsMichael Brown2025-07-096-12/+221
* [riscv] Support explicit cache management operations on I/O buffersMichael Brown2025-07-072-0/+273
* [riscv] Add support for detecting T-Head vendor extensionsMichael Brown2025-07-073-0/+90
* [riscv] Create coherent DMA mapping for low 4GB of address spaceMichael Brown2025-07-041-2/+30
* [riscv] Construct invariant portions of page table outside the loopMichael Brown2025-07-041-48/+49
* [build] Allow for the existence of small-data sectionsMichael Brown2025-06-241-0/+6
* [riscv] Inhibit SBI console when a serial console is activeMichael Brown2025-06-231-0/+12
* [riscv] Serialise MMIO accesses with respect to each otherMichael Brown2025-06-221-4/+8
* [riscv] Write SBI console output to early UART, if enabledMichael Brown2025-06-122-0/+31
* [riscv] Maximise barrier effects of memory fencesMichael Brown2025-06-121-1/+1
* [riscv] Support T-Head CPUs using non-standard Memory Attribute ExtensionMichael Brown2025-06-021-7/+59
* [riscv] Do not set executable bit in early UART page mappingMichael Brown2025-06-021-1/+1
* [riscv] Add fences around early UART writesMichael Brown2025-06-021-0/+2
* [riscv] Zero SATP after any failed attempt to enable pagingMichael Brown2025-06-021-5/+7
* [riscv] Add support for a SiFive-compatible early UARTMichael Brown2025-05-271-2/+33
* [riscv] Support mapping early UARTs outside of the identity mapMichael Brown2025-05-271-4/+48
* [riscv] Add support for writing prefix debug messages direct to a UARTMichael Brown2025-05-271-0/+79
* [riscv] Create macros for writing characters to the debug consoleMichael Brown2025-05-271-17/+62
* [riscv] Ignore riscv,isa property in favour of direct CSR testingMichael Brown2025-05-262-13/+5Star
* [riscv] Support mapping I/O devices outside of the identity mapMichael Brown2025-05-263-0/+267
* [riscv] Include carriage returns in libprefix.S debug messagesMichael Brown2025-05-261-8/+8
* [riscv] Support older SBI implementationsMichael Brown2025-05-254-18/+111
* [riscv] Speed up memmove() when copying in forwards directionMichael Brown2025-05-212-59/+13Star
* [lkrn] Add basic support for the RISC-V Linux kernel image formatMichael Brown2025-05-201-0/+34
* [riscv] Use generic external heap based on the system memory mapMichael Brown2025-05-193-83/+0Star
* [fdtmem] Update to use the generic system memory map APIMichael Brown2025-05-161-2/+2
* [fdtmem] Record size of accessible physical address spaceMichael Brown2025-05-141-0/+1
* [riscv] Add a .pf32 build target for padded parallel flash imagesMichael Brown2025-05-131-0/+7
* [riscv] Perform a writability test before applying relocationsMichael Brown2025-05-131-8/+37
* [riscv] Avoid potentially overwriting the scratch area during relocationMichael Brown2025-05-131-5/+18
* [riscv] Add a .lkrn build target resembling a Linux kernel binaryMichael Brown2025-05-133-0/+131
* [riscv] Relocate to a safe physical address on startupMichael Brown2025-05-123-64/+217
* [riscv] Construct page tables based on link-time virtual addressesMichael Brown2025-05-121-3/+13
* [riscv] Allow apply_relocs() to use non-inline relocation recordsMichael Brown2025-05-122-10/+12
* [riscv] Return accessible physical address space size from enable_paging()Michael Brown2025-05-121-2/+20
* [fdtmem] Add ability to parse FDT memory map for a relocation addressMichael Brown2025-05-112-0/+14
* [riscv] Ensure that prefix_virt is aligned on an xlen boundaryMichael Brown2025-05-111-0/+1
* [riscv] Hold virtual address offset in the thread pointer registerMichael Brown2025-05-113-81/+113
* [riscv] Use load and store pseudo-instructions where possibleMichael Brown2025-05-092-10/+5Star
* [riscv] Add support for disabling 64-bit and 32-bit pagingMichael Brown2025-05-081-0/+137
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