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* [intel] Add PCI ID for I219-V and -LM 6 to 9HEADmasterChristian Nilsson2019-03-181-0/+8
| | | | | Signed-off-by: Christian Nilsson <nikize@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [sfc] Add support for X25xx adaptersMartin Habets2018-08-262-3/+11
| | | | | | | | | | The first adapters in this family are X2522-10, X2522-25, X2541 and X2542. These no longer use PCI BAR 0 for I/O, but use that for memory. In other words, BAR 2 on SFN8xxx adapters now becomes BAR 0. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intelxl] Add driver for Intel 40 Gigabit Ethernet NICsMichael Brown2018-07-172-0/+2315
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ethernet] Use standard 1500 byte MTU unless explicitly overriddenMichael Brown2018-07-172-0/+2
| | | | | | | | | | | | | Devices that support jumbo frames will currently default to the largest possible MTU. This assumption is valid for virtual adapters such as virtio-net, where the MTU must have been configured by a system administrator, but is unsafe in the general case of a physical adapter. Default to the standard Ethernet MTU, unless explicitly overridden either by the driver or via the ${netX/mtu} setting. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intelx] Add support for Intel X552 NICSteven Haber2018-07-071-0/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [icplus] Add driver for IC+ network cardSylvie Barlow2018-04-202-0/+1015
| | | | | Signed-off-by: Sylvie Barlow <sylvie.c.barlow@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [mii] Add mii_find()Sylvie Barlow2018-04-201-0/+25
| | | | | | | Add the function mii_find() in order to locate the PHY address. Signed-off-by: Sylvie Barlow <sylvie.c.barlow@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [mii] Separate concepts of MII interface and MII deviceMichael Brown2018-04-199-40/+70
| | | | | | | | | | | | | We currently have no generic concept of a PHY address, since all existing implementations simply hardcode the PHY address within the MII access methods. A bit-bashing MII interface will need to be provided with an explicit PHY address in order to generate the correct waveform. Allow for this by separating out the concept of a MII device (i.e. a specific PHY address attached to a particular MII interface). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [velocity] Fix usage of mii_read() and mii_write()Michael Brown2018-04-191-4/+4
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [rhine] Fix usage of mii_read()Michael Brown2018-04-191-2/+1Star
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intelx] Add PCI_ROM entry for Intel X553 NICRob Taglang2018-04-101-0/+1
| | | | | Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [efi] Provide Map_Mem() and associated UNDI callbacksMichael Brown2018-03-201-0/+163
| | | | | | | | | | | | | | | | | | | Some drivers are known to call the optional Map_Mem() callback without first checking that the callback exists. Provide a usable basic implementation of Map_Mem() along with the other callbacks that become mandatory if Map_Mem() is provided. Note that in theory the PCI I/O protocol is allowed to require multiple calls to Map(), with each call handling only a subset of the overall mapped range. However, the reference implementation in EDK2 assumes that a single Map() will always suffice, so we can probably make the same simplifying assumption here. Tested with the Intel E3522X2.EFI driver (which, incidentally, fails to cleanly remove one of its mappings). Originally-implemented-by: Maor Dickman <maord@mellanox.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add PCI_ROM entry for Intel i354 NICRob Taglang2018-03-151-0/+1
| | | | | Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Work around broken reset mechanism in i219 devicesMichael Brown2018-02-032-9/+31
| | | | | | | | | | | | | | | | | | | | The i219 appears to have a seriously broken reset mechanism. After any transmit or receive activity, resetting the card will break both the transmit and receive datapaths until the next PCI bus reset. The Linux and BSD drivers include a convoluted workaround authored by Intel which involves setting a bit in the undocumented FEXTNVM11 register, then transmitting a dummy 512-byte packet containing garbage data, then reconfiguring the receive descriptor prefetch thresholds and temporarily reenabling the receive datapath. The comments in the Intel fix do not even remotely match what the code actually does, and the code accidentally leaves the transmitter enabled after use. Experimentation suggests that an equivalent fix is to simply set the undocumented bit in FEXTNVM11 before enabling the transmit or receive descriptor rings. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ena] Fix spurious uninitialised variable warning on older versions of gccMichael Brown2018-01-171-31/+7Star
| | | | | | | | | | Some older versions of gcc (observed with gcc 4.7.2) report a spurious uninitialised variable warning in ena_get_device_attributes(). Work around this warning by manually inlining the relevant code (which has only a single call site). Reported-by: xbgmsharp <xbgmsharp@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [tg3] Add support for SerDes PHY initializationJoseph Wong2018-01-142-4/+1021
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [skel] Remove MII interfaceMichael Brown2018-01-142-60/+0Star
| | | | | | | Most drivers do not utilise an MII interface, since the link state is typically available directly from a memory-mapped register. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ena] Add driver for Amazon ENA virtual function NICMichael Brown2018-01-132-0/+1627
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add PCI device ID for X550-T2Janos Mattyasovszky2017-12-201-0/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [exanic] Add PCI device ID for another X40 variantPeter von Konigsmark2017-09-071-0/+1
| | | | | Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [exanic] Power up optical PHYs (if present)Peter von Konigsmark2017-09-072-0/+7
| | | | | Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [efi] Raise TPL when calling UNDI entry pointMichael Brown2017-09-051-0/+8
| | | | | | | | | The SnpDxe driver raises the task priority level to TPL_CALLBACK when calling the UNDI entry point. This does not appear to be a documented requirement, but we should probably match the behaviour of SnpDxe to minimise surprises to third party code. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add various PCI device IDsRichard Moore2017-08-221-0/+4
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [efi] Enumerate PCI BARs in same order as SnpDxeMichael Brown2017-07-211-2/+2
| | | | | | | | | | | | | | | | | | | The UEFI specification has an implicit and demonstrably incorrect requirement (in the Mem_IO() calling convention) that any UNDI network device has at most one memory BAR and one I/O BAR. Some UEFI platforms have been observed to report the existence of non-existent additional I/O BARs, causing iPXE to select the wrong BAR. This problem does not affect the SnpDxe driver, since that driver will always choose the lowest numbered existent BAR of each type. Adjust iPXE's behaviour to match that of SnpDxe, i.e. to always select the lowest numbered BAR(s). Debugged-by: Andreas Hammarskjöld <junior@2PintSoftware.com> Debugged-by: Adklei <adklei@realtek.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [lan78xx] Add driver for Microchip LAN78xx USB Ethernet NICsMichael Brown2017-07-102-0/+494
| | | | | Originally-implemented-by: Ravi Hegde <ravi.hegde@microchip.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [smsc75xx] Expose functionality shared with LAN78xx devicesMichael Brown2017-07-102-6/+13
| | | | | | | | The LAN78xx datapath is essentially identical to that of the SMSC75xx. Expose the transmit, poll, and bulk IN endpoint operations to allow for reuse by the LAN78xx driver. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [smscusb] Allow for alternative PHY register layoutsMichael Brown2017-07-106-24/+49
| | | | | | | The LAN78xx PHY interrupt source and mask registers do not match those used by the SMSC75xx and SMSC95xx. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [smscusb] Move non-inline register access functions to smscusb.cMichael Brown2017-07-102-49/+61
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [virtio] Support VIRTIO_NET_F_IOMMU_PLATFORMJason Wang2017-07-101-1/+2
| | | | | | | | | Since we don't enable IOMMU at all, we can then simply enable the IOMMU support by claiming the support of VIRITO_F_IOMMU_PLATFORM. This fixes booting failure when iommu_platform is set from qemu cli. Signed-off-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [smscusb] Add ability to read MAC address from OTPMichael Brown2017-07-072-1/+251
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [smsc75xx] Use common SMSC USB device functionalityMichael Brown2017-07-072-721/+127Star
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [smsc95xx] Use common SMSC USB device functionalityMichael Brown2017-07-072-778/+141Star
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [smscusb] Abstract out common SMSC USB device functionalityMichael Brown2017-07-072-0/+825
| | | | | | | | | The smsc75xx and smsc95xx drivers include a substantial amount of identical functionality, varying only in the base address of register sets. Abstract out this common functionality to allow code to be shared between the drivers. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add support for I219-V in 7th Gen Intel NUCJerone Young2017-07-051-0/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [exanic] Add driver for Exablaze ExaNIC cardsMichael Brown2017-06-242-0/+1168
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [ecm] Display invalid MAC address strings in debug messagesMichael Brown2017-06-141-1/+6
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Add INTEL_NO_PHY_RST for I219-VMika Tiainen2017-06-141-1/+1
| | | | | | Fix booting on HP EliteBook 820 G3. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xen] Provide 18 4kB receive buffers to work around xen-netback bugMichael Brown2017-05-192-15/+41
| | | | | | | | | | | | | | | The Xen network backend (xen-netback) suffered from a regression between upstream Linux kernels 3.18 and 4.2 inclusive, which would cause packet reception to fail unless at least 18 receive buffers were available. This bug was fixed in kernel commit 1d5d485 ("xen-netback: require fewer guest Rx slots when not using GSO"). Work around this bug in affected versions of xen-netback by providing the requisite 18 receive buffers. Reported-by: Taylor Schneider <tschneider@live.com> Tested-by: Taylor Schneider <tschneider@live.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [hyperv] Cope with Windows Server 2016 enlightenmentsMichael Brown2017-04-282-0/+62
| | | | | | | | | | | | | | | | | | | | | | | An "enlightened" external bootloader (such as Windows Server 2016's winload.exe) may take ownership of the Hyper-V connection before all INT 13 operations have been completed. When this happens, all VMBus devices are implicitly closed and we are left with a non-functional network connection. Detect when our Hyper-V connection has been lost (by checking the SynIC message page MSR). Reclaim ownership of the Hyper-V connection and reestablish any VMBus devices, without disrupting any existing iPXE state (such as IPv4 settings attached to the network device). Windows Server 2016 will not cleanly take ownership of an active Hyper-V connection. Experimentation shows that we can quiesce by resetting only the SynIC message page MSR; this results in a successful SAN boot (on a Windows 2012 R2 physical host). Choose to quiesce by resetting (almost) all MSRs, in the hope that this will be more robust against corner cases such as a stray synthetic interrupt occurring during the handover. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Do not enable ASDE on i350 backplane NICMichael Brown2017-04-162-2/+6
| | | | | | | | | | | | | | | | | | | | | On most Intel NICs, Auto-Speed Detection Enable (ASDE) can be used to automatically detect the correct link speed by sampling the link using the internal PHY. This feature is automatically inhibited when not appropriate for the physical link (e.g. when using internal SerDes mode on the 8254x). On the i350 datasheet ASDE is a reserved bit, but the relevant auto-speed detection hardware appears still to be present. However, enabling ASDE on the i350 1000BASE-KX backplane NIC seems to cause an immediate link failure. It is possible that the auto-speed detection hardware is still present, is not connected to a physical link, and is not inhibited from being applied in this mode. Work around this problem by adding an INTEL_NO_ASDE flag bit (analogous to INTEL_NO_PHY_RST), and applying this for the i350 backplane NIC. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [intel] Show original CTRL and STATUS values in debugging outputMichael Brown2017-04-141-4/+12
| | | | | | | | In situations where iPXE fails to reach link-up as expected, it is useful to know the original values of the CTRL and STATUS registers prior to our reset attempt. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [sfc] Add driver for Solarflare SFC8XXX adaptersMartin Habets2017-04-109-0/+5602
| | | | | | Signed-off-by: Martin Habets <mhabets@solarflare.com> Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [thunderx] Use ThunderxConfigProtocol to obtain board configurationAdamczyk, Konrad2017-03-312-110/+60Star
| | | | | | | | | | | | | | | | | | Following changes were introduced: - added GetBgxProp and GetLmacProp methods to ThunderxConfigProtocol - replaced direct BOARD_CFG access with usage of introduced methods - removed redundant BOARD_CFG - changed GUID of ThunderxConfigProtocol, as this is not compatible with previous version - changed UINTN* to UINT64* buffer type to fix issue on 32-bit platforms with MAC address This change allows us to avoid alignment of BOARD_CFG definitions every time it changes in UEFI. Signed-off-by: Konrad Adamczyk <konrad.adamczyk@cavium.com> Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [build] Avoid implicit-fallthrough warnings on GCC 7Michael Brown2017-03-295-0/+17
| | | | | | Reported-by: Vinson Lee <vlee@freedesktop.org> Reported-by: Liang Yan <lyan@suse.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [vxge] Fix use of stale I/O buffer on error pathMichael Brown2017-03-231-2/+2
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [sky2] Use 32-bit read to read Y2_VAUX_AVAILMike McCormack2017-03-232-2/+2
| | | | | | | | | | | B0_CTST is a 24bit register according to the vendor driver (sk98lin). A 16bit read on B0_CTST will always return 0 for Y2_VAUX_AVAIL (1<<16), so use a 32bit read when testing Y2_VAUX_AVAIL. [This patch is copied directly from the Linux kernel tree.] Signed-off-by: Mike McCormack <mikem@ring3k.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pcnet32] Eliminate redundant register readMichael Brown2017-03-231-2/+1Star
| | | | | | | | | | | | | | | | | | | | | The value of ( ( x & 0x0c00 ) | 0x0c00 ) is always 0x0c00 regardless of the value of x, and so the read_csr() is redundant. (There are no read side effects for this register, according to the datasheet.) This line of code originated in Linux kernel 2.3.19pre1 as a->write_csr(ioaddr, 80, a->read_csr(ioaddr, 80) | 0x0c00); and was modified in kernel 2.3.41pre4 to read a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); In the absence of commit messages, the intention of the code is unclear. However, the logic resulting in a fixed value of 0x0c00 has remained unaltered for over 17 years, and can probably be assumed to have the correct overall result. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [rtl818x] Fix resource leak on error pathMichael Brown2017-03-231-2/+6
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [sis190] Avoid NULL pointer dereferenceMichael Brown2017-03-221-1/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [w89c840] Avoid potential array overrunMichael Brown2017-03-221-1/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
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