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path: root/src/drivers/usb/xhci.c
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* [init] Show startup and shutdown function names in debug messagesMichael Brown2019-01-251-0/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Consume event TRB before reporting completion to USB coreMichael Brown2018-02-191-4/+4
| | | | | | | | | | | | | | | | Reporting a completion via usb_complete() will pass control outside the scope of xhci.c, and could potentially result in a further call to xhci_event_poll() before returning from usb_complete(). Since we currently update the event consumer counter only after calling usb_complete(), this can result in duplicate completions and consequent corruption of the submission TRB ring structures. Fix by updating the event ring consumer counter before passing control to usb_complete(). Reported-by: Andreas Hammarskjöld <junior@2PintSoftware.com> Tested-by: Andreas Hammarskjöld <junior@2PintSoftware.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Assume an invalid PSI table if any invalid PSI value is observedMichael Brown2018-01-291-23/+30
| | | | | | | | | | | Invalid protocol speed ID tables appear to be increasingly common in the wild, to the point that it is infeasible to apply an explicit XHCI_BAD_PSIV flag for each offending PCI device ID. Fix by assuming an invalid PSI table as soon as any invalid value is reported by the hardware. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Avoid accessing beyond end of endpoint context arrayMichael Brown2017-03-211-1/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Ensure that zero-length packets are not part of a TRB chainMichael Brown2015-12-071-0/+6
| | | | | | | | | | | | Some xHCI controllers (such as qemu's emulated xHCI controller) do not correctly handle zero-length packets that are part of a TRB chain. The zero-length TRB ends up being squashed and does not result in a zero-length packet as seen by the device. Work around this problem by marking the zero-length packet as belonging to a separate transfer descriptor. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Record USB device speed separately from current port speedMichael Brown2015-12-071-2/+1Star
| | | | | | | | | | | | | Record the speed of a USB device based on the port's speed at the time that the device was enabled. This allows us to remember the device's speed even after the device has been disconnected (and so the port's current speed has changed). In particular, this allows us to correctly identify the transaction translator for a low-speed or full-speed device after the device has been disconnected. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Support arbitrarily large transfersMichael Brown2015-09-131-11/+45
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Generalise zero-length packet generation logicMichael Brown2015-09-131-3/+3
| | | | | | | | The decision on whether or not a zero-length packet needs to be transmitted is independent of the host controller and belongs in the USB core. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Ignore invalid protocol speed ID values on Intel Skylake platformsMichael Brown2015-06-181-3/+6
| | | | | | | | | | | | | | | Some Intel Skylake platforms (observed on a prototype Lenovo ThinkPad) report the list of available USB3 protocol speed ID values as {1,2,3} but then report a port's speed using ID value 4. The value 4 happens to be the default value for SuperSpeed (when no protocol speed ID value list is explicitly defined), and the hardware seems to function correctly if we simply ignore its protocol speed ID table and assume that it uses the default values. Fix by adding a "broken PSI values" quirk for this controller. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Record device-specific quirks in xHCI device structureMichael Brown2015-06-181-3/+4
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Fix comparison of signed and unsigned integersMichael Brown2015-06-011-1/+1
| | | | | | | | gcc 4.8.2 fails to report this erroneous comparison unless assertions are enabled. Reported-by: Mary-Ann Johnson <MaryAnn.Johnson@displaylink.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Fix length of allocated slot arrayMichael Brown2015-06-011-2/+3
| | | | | | | | | The xHCI slot ID is one-based, not zero-based. Fix the length of the xhci->slot[] array to account for this, and add assertions to check that the hardware returns a valid slot ID in response to the Enable Slot command. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Use meaningful device names in debug messagesMichael Brown2015-05-101-119/+122
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Detect missed disconnectionsMichael Brown2015-05-081-40/+49
| | | | | | | | | | | | | | | | | | | | | The USB core will currently fail to detect disconnections if a new device has attached by the time the port is examined in usb_hotplug(). Fix by recording the fact that a disconnection has taken place whenever the "connection status changed" (CSC) bit is observed to be set. (Whether the change represents a disconnection or a reconnection, it indicates that the port has experienced some time of being disconnected.) Note that the time at which a disconnection can be detected varies by hub type. In particular: root hubs can observe the CSC bit when polling, and so will record the disconnection before calling usb_port_changed(), but USB hubs read the port status (and hence the CSC bit) only during the call to hub_speed(), long after the call to usb_port_changed(). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pci] Provide PCI_CLASS() to calculate a scalar PCI class valueMichael Brown2015-05-081-2/+2
| | | | | | | | Rename PCI_CLASS() (which constructs a struct pci_class_id) to PCI_CLASS_ID(), and provide PCI_CLASS() as a macro which constructs the 24-bit scalar value of a PCI class code. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Include setup packet within I/O buffer for message transfersMichael Brown2015-05-011-4/+8
| | | | | | | | | | | | | | The USB API currently assumes that host controllers will have immediate data buffer space available in which to store the setup packet. This is true for xHCI, partially true for EHCI (which happens to have 12 bytes of padding in each transfer descriptor due to alignment requirements), and not true at all for UHCI. Include the setup packet within the I/O buffer passed to the host controller's message() method, thereby eliminating the requirement for host controllers to provide immediate data buffers. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Always reset root hub portsMichael Brown2015-04-131-7/+5Star
| | | | | | | | In theory USB3 ports do not require a reset to enable the port. Experimentation shows that this is sometimes required, particularly when rerouting ports from EHCI to xHCI and switching speeds. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Support USB1 devices attached via transaction translatorsMichael Brown2015-03-231-13/+73
| | | | | | | | | | | | | | | | | | | | xHCI provides a somewhat convoluted mechanism for specifying details of a transaction translator. Hubs must be marked as such in the device slot context. The only opportunity to do so is as part of a Configure Endpoint command, which can be executed only when opening the hub's interrupt endpoint. We add a mechanism for host controllers to intercept the opening of hub devices, providing xHCI with an opportunity to update the internal device slot structure for the corresponding USB device to indicate that the device is a hub. We then include the hub-specific details in the input context whenever any Configure Endpoint command is issued. When a device is opened, we record the device slot and port for its transaction translator (if any), and supply these as part of the Address Device command. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Add clear_tt() hub method to clear transaction translator bufferMichael Brown2015-03-231-0/+20
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Ring doorbell as part of endpoint resetMichael Brown2015-03-231-0/+3
| | | | | | | | | The endpoint may already have enqueued TRBs at the time that xhci_endpoint_reset() is called. Ring the doorbell to resume processing these TRBs immediately, rather than waiting until the next call to xhci_endpoint_message() or xhci_endpoint_stream(). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Do not release ownership back to BIOS when booting an OSMichael Brown2015-03-181-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xHCI (and EHCI) nominally provide a mechanism for releasing ownership of the host controller back to the BIOS, which can then potentially restore legacy USB keyboard functionality. This is a rarely used code path, since most operating systems claim ownership and never attempt to later return to the BIOS. On some systems (observed with a Lenovo X1 Carbon), this code path leads to obscure and interesting bugs: if the xHCI and EHCI controllers are both claimed and later released back to the BIOS, then a subsequent call to INT 16,0305 to set the keyboard repeat rate to a non-default value will lock the system. Obscure though this sequence of operations may sound, it is exactly what happens when using iPXE to boot a Linux kernel via a USB network card. There is old and probably unwanted code in Linux's arch/x86/boot/main.c which sets the keyboard repeat rate (with the accompanying comment "Set keyboard repeat rate (why?)"). When booting Linux via a USB network card on a Lenovo X1 Carbon, the system therefore locks up immediately after jumping to the kernel's entry point. Work around this problem by preventing the release of ownership back to the BIOS if it is known that we are shutting down to boot an OS. This should allow legacy USB keyboard functionality to be restored if the user chooses to exit iPXE, while avoiding the rarely used code paths (and corresponding BIOS bugs) if the user chooses instead to boot an OS. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Forcibly disable SMIs if BIOS fails to release ownershipMichael Brown2015-03-161-10/+10
| | | | | | | | If the BIOS fails to gracefully release ownership of the xHCI controller, we can forcibly claim it by disabling all SMIs via the USB legacy support control/status register. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Add the concept of a USB bus maximum transfer sizeMichael Brown2015-03-161-1/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Undo PCH-specific quirk fixes when removing deviceMichael Brown2015-03-061-2/+25
| | | | | | | | Restore the original values of XUSB2PR and USB3PSSEN, in case we are booting an OS with no support for xHCI. Suggested-by: Dan Ellis <Dan.Ellis@displaylink.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Enable USB3 ports on Intel PCH8/PCH9 controllersMichael Brown2015-03-061-0/+40
| | | | | | | | | | Intel PCH controllers default to routing USB2 ports to EHCI rather than xHCI, and default to disabling SuperSpeed connections. Manipulate the PCI configuration space registers as necessary to reroute ports and enable SuperSpeed. Originally-fixed-by: Dan Ellis <Dan.Ellis@displaylink.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [legal] Relicense files under GPL2_OR_LATER_OR_UBDLMichael Brown2015-03-021-1/+5
| | | | | | | Relicense files for which I am the sole author (as identified by util/relicense.pl). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Abort commands on timeoutMichael Brown2015-02-181-13/+69
| | | | | | | | | | | | When a command times out, abort it (via the Command Abort bit in the Command Ring Control Register) so that subsequent commands may execute as expected. This improves robustness when a device fails to respond to the Set Address command, since the subsequent Disable Slot command will now succeed. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Leak memory if controller fails to disable slotMichael Brown2015-02-181-3/+18
| | | | | | | | | | | | | | | | If the Disable Slot command fails then the hardware may continue to write to the slot context. Leak the memory used by the slot context to avoid future memory corruption. This situation has been observed in practice when a Set Address command fails, causing the command ring to become temporarily unresponsive. Note that there is no need to similarly leak memory on the failure path in xhci_device_open(), since in the event of a failure the hardware is never informed of the slot context address. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [xhci] Delay after (possibly) forcing port link state to RxDetectMichael Brown2015-02-111-0/+5
| | | | | | | | | | | | Some xHCI controllers (observed with a Renesas Electronics PCIe USB3 card) seem to require a delay after forcing the link state of USB3 ports to RxDetect. Omitting this delay causes strange behaviour including system lockups. Add an unconditional 20ms delay after writing the port link states. This seems to be sufficient to avoid the problem. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Allow usb_stream() to enforce a terminating short packetMichael Brown2015-02-101-6/+16
| | | | | | | | | | Some USB endpoints require that a short packet be used to terminate transfers, since they have no other way to determine message boundaries. If the message length happens to be an exact multiple of the USB packet size, then this requires the use of an additional zero-length packet. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Parse endpoint descriptor bInterval fieldMichael Brown2015-02-101-0/+10
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Report xHCI host controller eventsMichael Brown2015-02-051-0/+20
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [usb] Add support for xHCI host controllersMichael Brown2015-02-031-0/+3009
Signed-off-by: Michael Brown <mcb30@ipxe.org>
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