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| author | Alex Frid | 2017-07-25 12:34:07 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2017-08-24 00:59:24 +0200 |
| commit | a851ea2b9e1084a7bb02403ca03667e162e226fe (patch) | |
| tree | ebd8c577f1bea603f2b6a84c4c92d3d09bdd5624 | |
| parent | clk: tegra: Init cfg structure in _get_pll_mnp (diff) | |
| download | kernel-qcow2-linux-a851ea2b9e1084a7bb02403ca03667e162e226fe.tar.gz kernel-qcow2-linux-a851ea2b9e1084a7bb02403ca03667e162e226fe.tar.xz kernel-qcow2-linux-a851ea2b9e1084a7bb02403ca03667e162e226fe.zip | |
clk: tegra: Fix T210 effective NDIV calculation
Don't take the fractional part into account to calculate the effective
NDIV if fractional ndiv is not enabled.
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index dc4a81328d5a..a4d7d94b6436 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -241,6 +241,9 @@ #define PLL_SDM_COEFF BIT(13) #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) +/* This macro returns ndiv effective scaled to SDM range */ +#define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \ + (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0)) /* Tegra CPU clock and reset control regs */ #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 @@ -1288,8 +1291,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, s -= PLL_SDM_COEFF / 2; cfg->sdm_data = sdin_din_to_data(s); } - cfg->output_rate *= cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 + - sdin_data_to_din(cfg->sdm_data); + cfg->output_rate *= sdin_get_n_eff(cfg); cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF; } else { cfg->output_rate *= cfg->n; @@ -1314,8 +1316,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, */ static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg) { - cfg->n = cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 + - sdin_data_to_din(cfg->sdm_data); + cfg->n = sdin_get_n_eff(cfg); cfg->m *= PLL_SDM_COEFF; } |