diff options
| author | Stepan Moskovchenko | 2010-11-13 04:29:48 +0100 |
|---|---|---|
| committer | Daniel Walker | 2010-11-30 22:53:45 +0100 |
| commit | c4bd2eebee37b885b47ec48961923b671148703f (patch) | |
| tree | a0257c00f0aa720608ff6f173fa4f2566d33fc4b /arch/arm/mach-msm/include/mach/irqs-8x60.h | |
| parent | msm: iommu: Increase maximum MID size to 5 bits (diff) | |
| download | kernel-qcow2-linux-c4bd2eebee37b885b47ec48961923b671148703f.tar.gz kernel-qcow2-linux-c4bd2eebee37b885b47ec48961923b671148703f.tar.xz kernel-qcow2-linux-c4bd2eebee37b885b47ec48961923b671148703f.zip | |
msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU
Add register addresses and IRQ numbers for the IOMMU used
for the second 2D graphics core.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/include/mach/irqs-8x60.h')
| -rw-r--r-- | arch/arm/mach-msm/include/mach/irqs-8x60.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h index 36074cfc9ad2..f65841c74c0b 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x60.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h @@ -237,7 +237,12 @@ #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) #define INT_UART12DM_IRQ (GIC_SPI_START + 195) #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) -/*SPI 197 to 216 arent used in 8x60*/ + +/*SPI 197 to 209 arent used in 8x60*/ +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) + +/*SPI 212 to 216 arent used in 8x60*/ #define SMPSS_SPARE_1 (GIC_SPI_START + 217) #define SMPSS_SPARE_2 (GIC_SPI_START + 218) #define SMPSS_SPARE_3 (GIC_SPI_START + 219) |