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| author | Dinh Nguyen | 2019-08-14 17:30:14 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2019-08-14 18:23:21 +0200 |
| commit | c7ec75ea4d5316518adc87224e3cff47192579e7 (patch) | |
| tree | cf349df383621c280409c7788127b939ea6b90d8 /drivers/clk/clk.c | |
| parent | clk: samsung: exynos542x: Move MSCL subsystem clocks to its sub-CMU (diff) | |
| download | kernel-qcow2-linux-c7ec75ea4d5316518adc87224e3cff47192579e7.tar.gz kernel-qcow2-linux-c7ec75ea4d5316518adc87224e3cff47192579e7.tar.xz kernel-qcow2-linux-c7ec75ea4d5316518adc87224e3cff47192579e7.zip | |
clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk.c')
0 files changed, 0 insertions, 0 deletions