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author | Icenowy Zheng | 2016-12-13 16:22:47 +0100 |
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committer | Maxime Ripard | 2017-01-02 22:24:55 +0100 |
commit | 790d929b540661945d1c70652ffb602c5c06ad85 (patch) | |
tree | b224741b61032a0f7a2810797dd62210adb4773a /drivers/clk/mediatek | |
parent | clk: sunxi-ng: fix PLL_CPUX adjusting on H3 (diff) | |
download | kernel-qcow2-linux-790d929b540661945d1c70652ffb602c5c06ad85.tar.gz kernel-qcow2-linux-790d929b540661945d1c70652ffb602c5c06ad85.tar.xz kernel-qcow2-linux-790d929b540661945d1c70652ffb602c5c06ad85.zip |
clk: sunxi-ng: fix PLL_CPUX adjusting on A33
When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high,
and the system hangs.
Add a notifier to avoid this situation by temporarily switching to a
known stable 24 MHz oscillator.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions