diff options
| author | Shawn Lin | 2018-03-21 03:39:19 +0100 |
|---|---|---|
| committer | Heiko Stuebner | 2018-03-23 08:49:35 +0100 |
| commit | 4b0556a441dd37e598887215bc89b49a6ef525b3 (patch) | |
| tree | 683baf2164de1a4b82fafcd8eefdf90995de704c /drivers/clk/rockchip | |
| parent | clk: rockchip: Add 1.6GHz PLL rate for rk3399 (diff) | |
| download | kernel-qcow2-linux-4b0556a441dd37e598887215bc89b49a6ef525b3.tar.gz kernel-qcow2-linux-4b0556a441dd37e598887215bc89b49a6ef525b3.tar.xz kernel-qcow2-linux-4b0556a441dd37e598887215bc89b49a6ef525b3.zip | |
clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase
if clock rate is zero") catches one gremlin again for clk-rk3228.c
that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
sclk_sdmmc. However, the naming of the sdmmc clocks varies in the
manual with the card clock having the 0 while the hclk is named
without appended 0. So standardize one one format to prevent
confusion, as there also is only one (non-sdio) mmc controller on
the soc.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3228.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index 11e7f2d1c054..7af48184b022 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -387,7 +387,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), - COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), |