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path: root/drivers/clk/rockchip
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-178-46/+27Star
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| * clk: rockchip: export HDMIPHY clock on rk3228Heiko Stuebner2019-06-271-1/+1
| * clk: rockchip: add watchdog pclk on rk3328Heiko Stuebner2019-06-271-0/+3
| * clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macroHeiko Stuebner2019-06-154-36/+12Star
| * clk: rockchip: add a type from SGRF-controlled gate clocksHeiko Stuebner2019-06-141-0/+4
| * clk: rockchip: Remove 48 MHz PLL rate from rk3288Douglas Anderson2019-06-061-1/+0Star
| * clk: rockchip: add 1.464GHz cpu-clock rate to rk3228Justin Swartz2019-05-201-0/+1
| * clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()Douglas Anderson2019-05-201-3/+3
| * clk: rockchip: Don't yell about bad mmc phases when gettingDouglas Anderson2019-05-201-3/+1Star
| * clk: rockchip: Use clk_hw_get_rate() in MMC phase calculationDouglas Anderson2019-05-201-2/+2
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1Star
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner2019-06-051-11/+1Star
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-3017-170/+17Star
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* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-1512-1/+13
*-. Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' a...Stephen Boyd2019-05-074-26/+60
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| | * clk: rockchip: undo several noc and special clocks as critical on rk3288Douglas Anderson2019-04-231-9/+4Star
| | * clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-typeFinley Xiao2019-04-122-3/+29
| | * clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288Douglas Anderson2019-04-121-0/+11
| | * clk: rockchip: Limit use of USB PHY clock to USB on rk3288Matthias Kaehlcke2019-04-121-2/+2
| | * clk: rockchip: Fix video codec clocks on rk3288Douglas Anderson2019-04-121-2/+2
| | * clk: rockchip: Make rkpwm a critical clock on rk3288Douglas Anderson2019-04-111-1/+3
| | * clk: rockchip: fix wrong clock definitions for rk3328Jonas Karlman2019-03-181-9/+9
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* / clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2019-04-232-4/+4
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* clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclksFinley Xiao2019-01-071-2/+2
* clk: rockchip: fix frac settings of GPLL clock for rk3328Katsuhiro Suzuki2019-01-071-6/+6
* clk: rockchip: add clock-id to gate of ACODEC for rk3328Katsuhiro Suzuki2018-11-261-1/+1
* clk: rockchip: fix I2S1 clock gate register for rk3328Katsuhiro Suzuki2018-11-191-1/+1
* clk: rockchip: make rk3188 hclk_vio_bus criticalMark Yao2018-11-151-1/+2
* clk: rockchip: fix rk3188 sclk_mac_lbtest parameter orderingHeiko Stuebner2018-11-151-2/+2
* clk: rockchip: fix rk3188 sclk_smc gate dataFinley Xiao2018-11-151-2/+2
* clk: rockchip: fix typo in rk3188 spdif_frac parentJohan Jonker2018-11-121-1/+1
* clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent callEnric Balletbo i Serra2018-10-171-4/+0Star
* clk: rockchip: use the newly added clock-id for hdmi on RK3066Heiko Stuebner2018-10-111-1/+1
* clk: rockchip: fix wrong mmc sample phase shift for rk3328Ziyuan Xu2018-10-111-4/+4
* clk: rockchip: improve rk3288 pll rates for better hdmi outputUrja Rannikko2018-08-311-4/+25
* clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399Levin Du2018-08-061-0/+1
* clk: rockchip: fix clk_i2sout parent selection bits on rk3399Alberto Panizzo2018-07-081-1/+1
* clk: rockchip: add clock controller for px30Elaine Zhang2018-07-063-1/+1080
* clk: rockchip: add support for half dividerElaine Zhang2018-07-064-0/+323
* clk: rockchip: remove deprecated gate-clk code and dt-bindingHeiko Stuebner2018-05-232-99/+0Star
* clk: rockchip: use match_string() helperYisheng Xie2018-05-221-11/+5Star
* clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399Lin Huang2018-03-231-2/+2
* clk: rockchip: Fix error return in phase clock registrationShawn Lin2018-03-231-2/+4
* clk: rockchip: Correct the behaviour of restoring cached phaseShawn Lin2018-03-231-2/+14
* clk: rockchip: Fix wrong parents for MMC phase clock for rk3328Shawn Lin2018-03-231-8/+8
* clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228Shawn Lin2018-03-231-1/+1
* clk: rockchip: Add 1.6GHz PLL rate for rk3399Derek Basehore2018-03-141-0/+1
* clk: rockchip: Restore the clock phase after the rate was changedShawn Lin2018-03-131-1/+38
* clk: rockchip: Prevent calculating mmc phase if clock rate is zeroShawn Lin2018-03-051-0/+23
* clk: rockchip: Free the memory on the error pathShawn Lin2018-03-021-4/+18
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-05-19 04:04:46 +0200