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| author | Alberto Panizzo | 2018-07-06 15:18:51 +0200 |
|---|---|---|
| committer | Heiko Stuebner | 2018-07-08 00:19:19 +0200 |
| commit | a64ad008980c65d38e6cf6858429c78e6b740c41 (patch) | |
| tree | 2a01e321c68fceb9992be82b9efb1bf767d84c99 /drivers/clk/rockchip | |
| parent | clk: rockchip: add clock controller for px30 (diff) | |
| download | kernel-qcow2-linux-a64ad008980c65d38e6cf6858429c78e6b740c41.tar.gz kernel-qcow2-linux-a64ad008980c65d38e6cf6858429c78e6b740c41.tar.xz kernel-qcow2-linux-a64ad008980c65d38e6cf6858429c78e6b740c41.zip | |
clk: rockchip: fix clk_i2sout parent selection bits on rk3399
Register, shift and mask were wrong according to datasheet.
Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Cc: stable@vger.kernel.org
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3399.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index bca10d618f0a..2a8634a52856 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -631,7 +631,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, - RK3399_CLKSEL_CON(30), 8, 2, MFLAGS, + RK3399_CLKSEL_CON(31), 2, 1, MFLAGS, RK3399_CLKGATE_CON(8), 12, GFLAGS), /* uart */ |