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| author | Heiko Stuebner | 2018-11-15 12:17:30 +0100 |
|---|---|---|
| committer | Heiko Stuebner | 2018-11-15 12:19:09 +0100 |
| commit | ac8cb53829a6ba119082e067f5bc8fab3611ce6a (patch) | |
| tree | 69bf639c40dcac0b97729b4935f82780bee04803 /drivers/clk/rockchip | |
| parent | clk: rockchip: fix rk3188 sclk_smc gate data (diff) | |
| download | kernel-qcow2-linux-ac8cb53829a6ba119082e067f5bc8fab3611ce6a.tar.gz kernel-qcow2-linux-ac8cb53829a6ba119082e067f5bc8fab3611ce6a.tar.xz kernel-qcow2-linux-ac8cb53829a6ba119082e067f5bc8fab3611ce6a.zip | |
clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
Similar to commit a9f0c0e56371 ("clk: rockchip: fix rk3188 sclk_smc
gate data") there is one other gate clock in the rk3188 clock driver
with a similar wrong ordering, the sclk_mac_lbtest. So fix it as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3188.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index dee13dd20ba4..7c6af8e25b0c 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -362,8 +362,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKGATE_CON(2), 5, GFLAGS), MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), - GATE(0, "sclk_mac_lbtest", "sclk_macref", - RK2928_CLKGATE_CON(2), 12, 0, GFLAGS), + GATE(0, "sclk_mac_lbtest", "sclk_macref", 0, + RK2928_CLKGATE_CON(2), 12, GFLAGS), COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, |