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| author | Paulo Zanoni | 2018-07-25 02:28:12 +0200 |
|---|---|---|
| committer | Paulo Zanoni | 2018-07-25 22:41:42 +0200 |
| commit | 340a44bef2342b0ff7334017e9e821645fa8ae43 (patch) | |
| tree | d58ca1fd131a5e1b0389dbd834d76afe5a9d28ba /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/icl: Update FIA supported lane count for hpd. (diff) | |
| download | kernel-qcow2-linux-340a44bef2342b0ff7334017e9e821645fa8ae43.tar.gz kernel-qcow2-linux-340a44bef2342b0ff7334017e9e821645fa8ae43.tar.xz kernel-qcow2-linux-340a44bef2342b0ff7334017e9e821645fa8ae43.zip | |
drm/i915/icl: program MG_DP_MODE
Programming this register is part of the Enable Sequence for
DisplayPort on ICL. Do as the spec says.
v2: Simple rebase.
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180725002813.6938-5-paulo.r.zanoni@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 72acecaad5c1..cf1d2bbb0613 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2092,6 +2092,21 @@ enum i915_power_well_id { #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25) #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24) +#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0 +#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0 +#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0 +#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0 +#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0 +#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 +#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 +#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 +#define MG_DP_MODE(port, ln) \ + MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \ + MG_DP_MODE_LN0_ACU_PORT2, \ + MG_DP_MODE_LN1_ACU_PORT1) +#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) +#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6) + /* The spec defines this only for BXT PHY0, but lets assume that this * would exist for PHY1 too if it had a second channel. */ |