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| author | Ville Syrjälä | 2015-03-05 20:19:52 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-03-17 22:30:16 +0100 |
| commit | fc1ac8dee1fe3d3155e8622e4d8e9130d88bc65b (patch) | |
| tree | ac6a2222a0de9d68401ce2ec7fa2d53f3e64949b /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV (diff) | |
| download | kernel-qcow2-linux-fc1ac8dee1fe3d3155e8622e4d8e9130d88bc65b.tar.gz kernel-qcow2-linux-fc1ac8dee1fe3d3155e8622e4d8e9130d88bc65b.tar.xz kernel-qcow2-linux-fc1ac8dee1fe3d3155e8622e4d8e9130d88bc65b.zip | |
drm/i915: Disable DDR DVFS on CHV
DDR DVFS introduces massive memory latencies which can't be handled by
the PND deadline stuff. Instead the watermarks will need to be
programmed to compensate for the latency and the deadlines will need to
be programmed to tight fixed values. That means DDR DVFS can only be
enabled if the display FIFOs are large enough, and that pretty much
means we have to manually repartition them to suit the needs of the
moment.
That's a lot of change, so in the meantime let's just disable DDR DVFS
to get the display(s) to be stable.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b43de97f12da..495b22b4ec78 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -644,6 +644,11 @@ enum skl_disp_power_wells { #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 +#define PUNIT_REG_DDR_SETUP2 0x139 +#define FORCE_DDR_FREQ_REQ_ACK (1 << 8) +#define FORCE_DDR_LOW_FREQ (1 << 1) +#define FORCE_DDR_HIGH_FREQ (1 << 0) + #define PUNIT_GPU_STATUS_REG 0xdb #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff |