diff options
| author | Suzuki K Poulose | 2017-08-02 18:22:14 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2017-08-28 16:05:49 +0200 |
| commit | cd407abd5efd6f36b6372d615fbab486936e90f4 (patch) | |
| tree | 1f2f04f34ef21401c540b622c7dfec93e424d655 /drivers/hwtracing/coresight/coresight-tmc-etr.c | |
| parent | coresight tmc etr: Detect address width at runtime (diff) | |
| download | kernel-qcow2-linux-cd407abd5efd6f36b6372d615fbab486936e90f4.tar.gz kernel-qcow2-linux-cd407abd5efd6f36b6372d615fbab486936e90f4.tar.xz kernel-qcow2-linux-cd407abd5efd6f36b6372d615fbab486936e90f4.zip | |
coresight tmc etr: Cleanup AXICTL register handling
This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-tmc-etr.c')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 9c39c899ebd5..880b53527599 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -36,13 +36,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); axictl = readl_relaxed(drvdata->base + TMC_AXICTL); - axictl |= TMC_AXICTL_WR_BURST_16; - writel_relaxed(axictl, drvdata->base + TMC_AXICTL); - axictl &= ~TMC_AXICTL_SCT_GAT_MODE; - writel_relaxed(axictl, drvdata->base + TMC_AXICTL); - axictl = (axictl & - ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) | - TMC_AXICTL_PROT_CTL_B1; + axictl &= ~TMC_AXICTL_CLEAR_MASK; + axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16); + axictl |= TMC_AXICTL_AXCACHE_OS; writel_relaxed(axictl, drvdata->base + TMC_AXICTL); tmc_write_dba(drvdata, drvdata->paddr); |