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authorHou Zhiqiang2019-07-05 11:56:38 +0200
committerLorenzo Pieralisi2019-07-08 13:28:44 +0200
commit6f3ab451aa5c2cbff33197d82fe8489cbd55ad91 (patch)
tree550934011745bc287c12f033cd96bbcdb4f19952 /drivers/pci/controller
parentPCI: mobiveil: Move IRQ chained handler setup out of DT parse (diff)
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PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers
The reset value of Primary, Secondary and Subordinate bus numbers is zero which is a broken setup. Program a sensible default value for Primary/Secondary/Subordinate bus numbers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Diffstat (limited to 'drivers/pci/controller')
-rw-r--r--drivers/pci/controller/pcie-mobiveil.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index cdf15cca526e..8f561300a88e 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -561,6 +561,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
u32 value, pab_ctrl, type = 0;
struct resource_entry *win;
+ /* setup bus numbers */
+ value = csr_readl(pcie, PCI_PRIMARY_BUS);
+ value &= 0xff000000;
+ value |= 0x00ff0100;
+ csr_writel(pcie, value, PCI_PRIMARY_BUS);
+
/*
* program Bus Master Enable Bit in Command Register in PAB Config
* Space