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| author | Zhou Wang | 2015-08-26 05:17:34 +0200 |
|---|---|---|
| committer | Bjorn Helgaas | 2015-09-18 20:54:21 +0200 |
| commit | ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e (patch) | |
| tree | 37ecaf3c7813f9c758be6430e0f82a0eb31a12d9 /drivers/pci/host/pcie-designware.c | |
| parent | Linux 4.3-rc1 (diff) | |
| download | kernel-qcow2-linux-ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e.tar.gz kernel-qcow2-linux-ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e.tar.xz kernel-qcow2-linux-ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e.zip | |
PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK
The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. In IP
v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8]
are defined for NUM_OF_LANES, bits [16:13] are for other usages (bit 16 is
AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE).
As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, change
the mask value to avoid future problems.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Diffstat (limited to 'drivers/pci/host/pcie-designware.c')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 52aa6e34002b..d72692610aee 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -35,7 +35,7 @@ #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) |