summaryrefslogtreecommitdiffstats
path: root/drivers/pci/host/pcie-designware.c
Commit message (Expand)AuthorAgeFilesLines
* PCI: Move DesignWare IP support to new drivers/pci/dwc/ directoryKishon Vijay Abraham I2017-02-211-902/+0Star
* PCI: designware: Check for iATU unroll only on platforms that use ATUMurali Karicheri2017-01-101-5/+5
* PCI: designware: Check for iATU unroll support after initializing hostNiklas Cassel2016-11-041-2/+5
* PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val argumentsBjorn Helgaas2016-10-111-16/+16
* PCI: designware: Uninline register accessorsBjorn Helgaas2016-10-111-2/+2
* PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc()Bjorn Helgaas2016-10-111-2/+2
* PCI: designware: Swap order of dw_pcie_writel_rc() reg/val argumentsBjorn Helgaas2016-10-111-24/+24
* PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfacesBjorn Helgaas2016-10-111-2/+2
* PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll()Kishon Vijay Abraham I2016-10-111-8/+2Star
* PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device()Bjorn Helgaas2016-10-061-4/+4
*-. Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-artpec', 'pc...Bjorn Helgaas2016-10-051-35/+141
|\ \
| | * PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs'Dong Bo2016-08-231-5/+5
| | * PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2Pratyush Anand2016-08-221-7/+19
| | * PCI: designware: Check LTSSM training bit before deciding link is upJisheng Zhang2016-08-181-2/+4
| | * PCI: designware: Add iATU Unroll featureJoao Pinto2016-08-171-11/+86
| | * PCI: designware: Wait for iATU enableJoao Pinto2016-08-171-3/+15
| | * PCI: designware: Move link wait definitions to .c fileJoao Pinto2016-08-171-0/+5
| | * PCI: designware: Return data directly from dw_pcie_readl_rc()Bjorn Helgaas2016-08-171-10/+10
| |/
* | Merge branch 'pci/virtualization' into nextBjorn Helgaas2016-10-031-7/+0Star
|\ \
| * | PCI: designware: Relax device number checking to allow SR-IOVPo Liu2016-09-121-7/+0Star
| |/
* | Merge branch 'pci/enumeration' into nextBjorn Helgaas2016-10-031-9/+12
|\ \
| * | PCI: designware: Fix pci_remap_iospace() failure pathLorenzo Pieralisi2016-09-061-9/+12
| |/
* / PCI: designware: Make explicitly non-modularPaul Gortmaker2016-08-231-5/+0Star
|/
* PCI: designware: Simplify host bridge window iterationBjorn Helgaas2016-06-201-5/+1Star
* PCI: designware: Request host bridge window resourcesBjorn Helgaas2016-06-201-0/+4
* PCI: designware: Free bridge resource list on failureBjorn Helgaas2016-06-201-7/+17
* PCI: designware: Remove incorrect RC memory base/limit configurationGabriele Paoloni2016-05-021-8/+0Star
* PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()Jisheng Zhang2016-04-061-20/+19Star
* PCI: designware: Add default link up check if sub-driver doesn't overrideJoao Pinto2016-03-151-1/+9
* PCI: designware: Add generic dw_pcie_wait_for_link()Joao Pinto2016-03-151-0/+19
* PCI: designware: Remove PCI_PROBE_ONLY handlingLorenzo Pieralisi2016-02-091-6/+4Star
* PCI: designware: Explain why we don't program ATU for some platformsJisheng Zhang2016-02-091-0/+5
* Merge tag 'pci-v4.5-changes' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2016-01-211-36/+26Star
|\
| *-. Merge branches 'pci/host', 'pci/host-designware', 'pci/host-hisi', 'pci/host-...Bjorn Helgaas2016-01-151-36/+26Star
| |\ \
| | | * PCI: designware: Ensure ATU is enabled before IO/conf space accessesStanimir Varbanov2016-01-051-0/+8
| | |/ | |/|
| | * PCI: designware: Make config accessor override checking symmetricBjorn Helgaas2016-01-111-6/+6
| | * PCI: designware: Simplify control flowBjorn Helgaas2016-01-051-36/+18Star
| |/
* / PCI: designware: Remove incorrect io_base assignmentStanimir Varbanov2015-11-241-1/+0Star
|/
* PCI: designware: Make driver arch-agnosticZhou Wang2015-11-021-91/+39Star
* PCI: designware: Use of_pci_get_host_bridge_resources() to parse DTZhou Wang2015-11-021-53/+46Star
* Revert "PCI: designware: Program ATU with untranslated address"Zhou Wang2015-11-021-30/+11Star
* PCI: designware: Move calculation of bus addresses to DRA7xxGabriele Paoloni2015-11-021-11/+4Star
* PCI: designware: Make "num-lanes" an optional DT propertyGabriele Paoloni2015-11-021-4/+6
* PCI: designware: Require config accesses to be naturally alignedGabriele Paoloni2015-11-021-0/+8
* PCI: designware: Simplify dw_pcie_cfg_read/write() interfacesGabriele Paoloni2015-11-021-16/+12Star
* PCI: designware: Use exact access size in dw_pcie_cfg_read()Gabriele Paoloni2015-11-021-6/+8
* PCI: designware: Set up high part of MSI target addressLucas Stach2015-11-021-5/+12
* PCI: designware: Implement multivector MSI IRQ setupLucas Stach2015-09-181-0/+31
* PCI: designware: Factor out MSI msg setupLucas Stach2015-09-181-11/+17
* PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASKZhou Wang2015-09-181-1/+1
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-14 18:42:04 +0200