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author | Dhaval Shah | 2017-12-21 19:33:06 +0100 |
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committer | Michal Simek | 2018-01-08 13:42:47 +0100 |
commit | cee8113a295acfc4cd25728d7c3d44e6bc3bbff9 (patch) | |
tree | 9f5bf6d034f9120fb26e46593fbab85dbf4cc8d0 /drivers/soc/xilinx/Makefile | |
parent | dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver (diff) | |
download | kernel-qcow2-linux-cee8113a295acfc4cd25728d7c3d44e6bc3bbff9.tar.gz kernel-qcow2-linux-cee8113a295acfc4cd25728d7c3d44e6bc3bbff9.tar.xz kernel-qcow2-linux-cee8113a295acfc4cd25728d7c3d44e6bc3bbff9.zip |
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
Xilinx ZYNQMP logicoreIP Init driver is based on the new
LogiCoreIP design created. This driver provides the processing system
and programmable logic isolation. Set the frequency based on the clock
information get from the logicoreIP register set.
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/soc/xilinx/Makefile')
-rw-r--r-- | drivers/soc/xilinx/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/soc/xilinx/Makefile b/drivers/soc/xilinx/Makefile index f66554cd5c45..dee8fd51e303 100644 --- a/drivers/soc/xilinx/Makefile +++ b/drivers/soc/xilinx/Makefile @@ -1 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o |