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| author | Dmitry Osipenko | 2019-06-18 16:03:58 +0200 |
|---|---|---|
| committer | Daniel Lezcano | 2019-06-25 19:49:18 +0200 |
| commit | 6fde3894e26ec53989b12162f11616029825a8c8 (patch) | |
| tree | 945d60aaf7c0f3eab4640c92ff49b2f3f86ced43 /include/clocksource | |
| parent | clocksource/drivers/tegra: Cycles can't be 0 (diff) | |
| download | kernel-qcow2-linux-6fde3894e26ec53989b12162f11616029825a8c8.tar.gz kernel-qcow2-linux-6fde3894e26ec53989b12162f11616029825a8c8.tar.xz kernel-qcow2-linux-6fde3894e26ec53989b12162f11616029825a8c8.zip | |
clocksource/drivers/tegra: Set up maximum-ticks limit properly
Tegra's timer has 29 bits for the counter and for the "load" register
which sets counter to a load-value. The counter's value is lower than
the actual value by 1 because it starts to decrement after one tick,
hence the maximum number of ticks that hardware can handle equals to
29 bits + 1.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'include/clocksource')
0 files changed, 0 insertions, 0 deletions