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| author | David S. Miller | 2019-06-07 01:24:30 +0200 |
|---|---|---|
| committer | David S. Miller | 2019-06-07 01:24:30 +0200 |
| commit | 96524ea4be04683bb3ad8ebaedcbe3a6e34302de (patch) | |
| tree | 1aa7e943c5d445b4eb21299ea3e3871a8027b59c /security | |
| parent | net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10 (diff) | |
| parent | net: axienet: convert to phylink API (diff) | |
| download | kernel-qcow2-linux-96524ea4be04683bb3ad8ebaedcbe3a6e34302de.tar.gz kernel-qcow2-linux-96524ea4be04683bb3ad8ebaedcbe3a6e34302de.tar.xz kernel-qcow2-linux-96524ea4be04683bb3ad8ebaedcbe3a6e34302de.zip | |
Merge branch 'Xilinx-axienet-driver-updates'
Robert Hancock says:
====================
Xilinx axienet driver updates (v5)
This is a series of enhancements and bug fixes in order to get the mainline
version of this driver into a more generally usable state, including on
x86 or ARM platforms. It also converts the driver to use the phylink API
in order to provide support for SFP modules.
Changes since v4:
-Use reverse christmas tree variable order
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'security')
0 files changed, 0 insertions, 0 deletions