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| author | Marek Szyprowski | 2017-01-26 13:37:53 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki | 2017-01-27 11:34:00 +0100 |
| commit | 698e0d1d22346ef03d7a13fcd9c2cc86a24bf317 (patch) | |
| tree | 4effec2a5d8cc0b65e1c9098537a7621491bfbf4 /virt | |
| parent | clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks (diff) | |
| download | kernel-qcow2-linux-698e0d1d22346ef03d7a13fcd9c2cc86a24bf317.tar.gz kernel-qcow2-linux-698e0d1d22346ef03d7a13fcd9c2cc86a24bf317.tar.xz kernel-qcow2-linux-698e0d1d22346ef03d7a13fcd9c2cc86a24bf317.zip | |
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure
such configuration for those boards with 'assigned-clock-*' properties,
parameters for those two additional rates are needed.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'virt')
0 files changed, 0 insertions, 0 deletions