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* MIPS: Netlogic: Add MSI support for XLPJayachandran C2014-01-2411-37/+586
| | | | | | | | | | | | | | | | | | | | | Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
* MIPS: malta: Incorporate PIIX4 ACPI I/O region in PCI controller resourcesDeng-Cheng Zhu2014-01-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot log says: pci 0000:00:0a.3: no compatible bridge window for [io 0x1000-0x103f] pci 0000:00:0a.3: no compatible bridge window for [io 0x1100-0x110f] The io resource starting point on Malta was modified by c5de50dada (MIPS: Malta: Change start address to avoid conflicts.) to avoid conflicts with ACPI and SMB devices. In fact, that was not needed (and now causing southbridge ACPI missing) since 166c637075 (PCI: add pci_create_root_bus() that accepts resource list) and 7c090e5bfa (mips/PCI: convert to pci_scan_root_bus() for correct root bus resources) had already done the correct fix. This patch actually reverts the change made by c5de50dada. And with this fix, log says: pci 0000:00:0a.3: quirk: [io 0x1000-0x103f] claimed by PIIX4 ACPI pci 0000:00:0a.3: quirk: [io 0x1100-0x110f] claimed by PIIX4 SMB These things may not be used but as part of platform resources are better off to be included. Cc: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6037/
* MIPS: /proc/cpuinfo: always print the supported ISAAaro Koskinen2014-01-241-20/+19Star
| | | | | | | | | Currently the supported ISA is only printed on the latest architectures. Print it also on legacy platforms. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6295/
* MIPS: jz4740: update platform data for JZ4740 usb device controllerApelete Seketeli2014-01-243-16/+26
| | | | | | | | | | | | | | | The platform data already available in tree for JZ4740 USB Device Controller was previously used by an out-of-tree USB gadget driver which was not relying on the musb driver and was written by Ingenic and the Qi-Hardware community. Update platform data for JZ4740 USB device controller to be used with musb driver. Signed-off-by: Apelete Seketeli <apelete@seketeli.net> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6265/
* MIPS: Kill CONFIG_MTD_PARTITIONSEunbong Song2014-01-2411-11/+0Star
| | | | | | | | | This patch removes CONFIG_MTD_PARTITIONS in config files for MIPS. Because CONFIG_MTD_PARTITIONS was removed by commit 6a8a98b22b10f1560d5f90aded4a54234b9b2724. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6162/ Signed-off-by: Eunbong Song <eunb.song@samsung.com>
* MIPS: replace open-coded init_dspPaul Burton2014-01-241-2/+1Star
| | | | | | | | | | | There is already an init_dsp function which checks cpu_has_dsp & calls __init_dsp if it does. Make use of it instead of duplicating the same code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6148/
* MIPS: clean up resume declarationPaul Burton2014-01-241-4/+12
| | | | | | | | | | | | This patch cleans up the declaration of the resume function by replacing void pointers with their correct types. The irrelevant & incorrect comment preceeding the resume function is replaced by one documenting its function. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6146/
* MIPS: qi_lb60: add defconfig for Ben NanoNoteApelete Seketeli2014-01-241-0/+188
| | | | | | | | | | Add defconfig for the Ben NanoNote handheld computer which is built around QI_LB60 board and Ingenic JZ4740 MIPS SoC. Signed-off-by: Apelete Seketeli <apelete@seketeli.net> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6257/
* bcma: gpio: add own IRQ domainRafał Miłecki2014-01-233-2/+134
| | | | | | | | | | | | | | Input GPIO changes can generate interrupts, but we need kind of ACK for them by changing IRQ polarity. This is required to stop hardware from keep generating interrupts and generate another one on the next GPIO state change. This code allows using GPIOs with standard interrupts and add for example GPIO buttons support. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6216/
* MIPS: include linux/types.hQais Yousef2014-01-231-0/+1
| | | | | | | | | | | | | | The file uses u16 type but doesn't include its definition explicitly I was getting this error when including this header in my driver: arch/mips/include/asm/mipsregs.h:644:33: error: unknown type name ‘u16’ Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6212/
* MIPS: sead3: use unflatten_and_copy_device_tree()Qais Yousef2014-01-231-10/+1Star
| | | | | | | | | | | we want the device tree to be unflattened into non init memory so it can be accessed later by, for example, a probing function of a driver module. Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6210/
* MIPS: sead3: populate platform devices from device treeQais Yousef2014-01-231-0/+7
| | | | | | | | Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6209/
* MIPS: sead3: remove chosen nodeQais Yousef2014-01-231-4/+0Star
| | | | | | | | | | | | | | | | | | | The defaults are not always applicable and it makes it hard for the bootloader to override them. By removing it we give the bootloader full control over what command line parameters to pass. Without this change we will need to modify the built-in dtb to add bootloader cmd line parameters or do some work to append them after we unflatten the device tree. Sead3 is a development board, that's why we want to be able to change boot parameters on the fly from the bootloader. Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6208/
* MIPS: sead3: allow cmdline/env to change memory size using memsize paramQais Yousef2014-01-233-0/+71
| | | | | | | | | | | if the user sets memsize parameter in commandline or bootloader environment, we use it to modify the built-in dtb memory size Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6207/
* MIPS: BCM63XX: use linux/serial_bcm63xx.hFlorian Fainelli2014-01-232-8/+1Star
| | | | | | | | | | | Update the early_printk code to include linux/serial_bcm63xx.h which provides the definitions for the UART block registers. While at it, remove the inclusion of serial_bcm63xx.h which was just there to allow smooth transition. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6203/
* tty: serial: bcm63xx_uart: use linux/serial_bcm63xx.hFlorian Fainelli2014-01-231-2/+1Star
| | | | | | | | | | Now that the UART block defines have been moved to a separate file, include that one and do not longer rely on the MIPS-specific bcm63xx_regs.h header file. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6204/
* MIPS: BCM63XX: move UART register definitionsFlorian Fainelli2014-01-232-114/+120
| | | | | | | | | | Move the BCM63XX UART driver definitions to include/linux/serial_bcm63xx.h such that we do not rely on the MIPS BCM63XX code to provide these for us. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6202/
* tty: serial: bcm63xx_uart: drop bcm_{readl,writel} macrosFlorian Fainelli2014-01-231-3/+2Star
| | | | | | | | | | | bcm_{readl,writel} macros expand to __raw_{readl,writel}, use these directly such that we do not rely on the platform to provide these for us. As a result, we no longer use bcm63xx_io.h, so remove that inclusion too. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6201/
* tty: serial: bcm63xx_uart: remove unused inclusionFlorian Fainelli2014-01-231-1/+0Star
| | | | | | | | | bcm63xx_irqs.h is included but we are not using anything from it, drop that include. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6205/
* MIPS: microMIPS: Remove unsupported compiler flag.Steven J. Hill2014-01-231-1/+1
| | | | | | | | | | | | Remove usage of -mno-jals compiler flag when building a pure microMIPS kernel. The -mno-jals flag only ever existed within Mentor toolchains. Dropping this flag allows all FSF toolchains to work. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6200/
* MIPS: OCTEON: Supply OCTEON+ USB nodes in internal device trees.David Daney2014-01-234-0/+87
| | | | | | | | | | This will be needed by the next patch to use said nodes for probing via the device tree. Signed-off-by: David Daney <david.daney@cavium.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6185/
* MIPS: Malta: use generic 8250 early consolePaul Burton2014-01-234-75/+33Star
| | | | | | | | | | | | | | | | | | | | | | | This patch switches Malta from using the MIPS implementation of early printk with Malta's prom_putchar to using the generic 8250_early implementation. This offers a couple of advantages: - We duplicate less generic code. - The UART can be initialised rather than being reliant upon inheriting a valid setup from the bootloader. The Malta console_config function is extended to initialise the early console if no earlycon= kernel parameter is provided, inheriting the modetty0 bootloader environment if present and falling back to a default 38400n8r setup if not. This matches the behaviour used for the regular console= parameter. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6183/
* MIPS: Malta: mux & enable SERIRQ interruptPaul Burton2014-01-232-0/+18
| | | | | | | | | | | | | | | This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ pin of the PIIX4 and to enable that interrupt. The kernel depends upon the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but previously would not configure it, instead relying upon the bootloader having done so. If that is not the case then the typical result is that the system appears to hang once it reaches userland as no output is displayed on the UART. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6182/
* MIPS: Malta: initialise the RTC at bootPaul Burton2014-01-231-0/+13
| | | | | | | | | | | | | | The RTC is used on Malta to estimate the clock frequency of the CPU & optionally the GIC. However the kernel previously did not initialise the RTC, instead relying upon the bootloader having done so. In order to minimise dependencies which the kernel has upon the bootloader this patch causes the kernel to initialise the RTC itself prior to making use of it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6184/
* MIPS: sead3: remove unused cpu_khz variablePaul Burton2014-01-231-4/+0Star
| | | | | | | | | | | This variable seems to have been copied from Malta when SEAD3 support was introduced, but is likewise unused. Remove it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6172/
* MIPS: Malta: remove unused cpu_khz variablePaul Burton2014-01-231-3/+0Star
| | | | | | | | | | | | This variable was introduced by commit 96348c8f (of Ralf's historic Linux/MIPS repository) "Remaining fixes for MIPS's eval boards." but I don't see any use of it either then or now. Remove it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6171/
* MIPS: cavium-octeon: export symbols needed by octeon-ethernetAaro Koskinen2014-01-235-1/+16
| | | | | | | | | | Export symbols needed by the octeon-ethernet driver. The patch fixes a build failure with CONFIG_OCTEON_ETHERNET=m. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6166/
* MIPS: Fix build error seen in some configurationsGuenter Roeck2014-01-231-1/+1
| | | | | | | | | | | | | | | The following build error is seen if CONFIG_32BIT is undefined, CONFIG_64BIT is defined, and CONFIG_MIPS32_O32 is undefined. asm/syscall.h: In function 'mips_get_syscall_arg': arch/mips/include/asm/syscall.h:32:16: error: unused variable 'usp' [-Werror=unused-variable] cc1: all warnings being treated as errors Fixes: c0ff3c53d4f9 ('MIPS: Enable HAVE_ARCH_TRACEHOOK') Signed-off-by: Guenter Roeck <linux@roeck-us.net> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6160/
* MIPS: cavium-octeon: fix early boot hang on EBH5600 boardAaro Koskinen2014-01-231-3/+3
| | | | | | | | | | | | | | | | The boot hangs early on EBH5600 board when octeon_fdt_pip_iface() is trying enumerate a non-existant interface. The actual hang happens in cvmx_helper_interface_get_mode(): mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); when interface == 4. We can avoid this situation by first checking that the interface exists in the DTB. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6101/
* MIPS: cavium-octeon: fix out-of-bounds array accessAaro Koskinen2014-01-231-1/+1
| | | | | | | | | | | When booting with in-kernel DTBs, the pruning code will enumerate interfaces 0-4. However, there is memory reserved only for 4 so some other data will get overwritten by cvmx_helper_interface_enumerate(). Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6102/
* MIPS: JZ4740: reuse UART0 address macro for vmlinuz debug portAntony Pavlov2014-01-231-2/+2
| | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5927/
* MIPS: improve checks for noncoherent DMAFelix Fietkau2014-01-224-5/+16
| | | | | | | | | | | Only one MIPS development board actually supports enabling/disabling DMA coherency at runtime, so it's not a good idea to push the overhead of checking that configuration setting onto every other supported target as well. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5912/
* MIPS: APRP: Code formatting clean-ups.Steven J. Hill2014-01-229-320/+248Star
| | | | | | | | | Clean-up code according to the 'checkpatch.pl' script. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6097/ Reviewed-by: John Crispin <blogic@openwrt.org>
* MIPS: APRP: Add support for Malta CMP platform.Deng-Cheng Zhu2014-01-223-5/+35
| | | | | | | | | | Malta with multi-core CM platforms can now use APRP functionality. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6096/
* MIPS: APRP: Add RTLX API support for CMP platforms.Deng-Cheng Zhu2014-01-224-0/+123
| | | | | | | | | | This patch adds RTLX API support for platforms having a CMP. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6095/ Reviewed-by: John Crispin <blogic@openwrt.org>
* MIPS: APRP: Split RTLX support into separate files.Deng-Cheng Zhu2014-01-225-144/+195
| | | | | | | | | | | | Split the RTLX functionality in preparation for adding support for CMP platforms. Common functions remain in the original file and a new file contains code specific to platforms that do not have a CMP. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6093/ Reviewed-by: John Crispin <blogic@openwrt.org>
* MIPS: APRP: Add VPE loader support for CMP platforms.Deng-Cheng Zhu2014-01-223-0/+186
| | | | | | | | | | This patch adds VPE loader support for platforms having a CMP. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6092/
* MIPS: APRP: Split VPE loader into separate files.Deng-Cheng Zhu2014-01-225-633/+660
| | | | | | | | | | | | | Split the VPE functionality in preparation for adding support for CMP platforms. Common functions remain in the original file and a new file contains code specific to platforms that do not have a CMP present. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6094/
* MIPS: Clean up MIPS MT and CMP configuration options.Steven J. Hill2014-01-222-40/+24Star
| | | | | | | | | | | | | | This patch accomplishes the following: * Clean up wording on all MIPS MT configuration menu items. * Simplify and neaten up options selected by MIPS_MT_SMP. * Make MIPS_MT_SMTC support as deprecated. * Make MIPS_CMP support to depend on MIPS_MT_SMP also. * Remove redundant options selected by MIPS_CMP. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6019/
* MIPS: kernel: cpu-probe: Add support for probing interAptiv coresLeonid Yegoshin2014-01-221-0/+8
| | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6152/
* MIPS: Add support for interAptiv coresLeonid Yegoshin2014-01-229-1/+12
| | | | | | | | | | | | | | | The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6163/
* MIPS: Add processor identifiers for the interAptiv processorsLeonid Yegoshin2014-01-221-0/+2
| | | | | | | | | Add processor identifiers for UP and MT interAptiv processors. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6151/
* MIPS: Add debugfs file to print the segmentation control registersSteven J. Hill2014-01-222-0/+111
| | | | | | | | | | | | | | | | | | | | | Add a new mips/segments debugfs file to print the 6 segmentation control registers for supported cores. A sample from a proAptiv core is given below: Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6137/ Segment Virtual Size Access Mode Physical Caching EU ------- ------- ---- ----------- -------- ------- -- 0 e0000000 512M MK UND U 0 1 c0000000 512M MSK UND U 0 2 a0000000 512M UK 000 2 0 3 80000000 512M UK 000 3 0 4 40000000 1G MUSK UND U 1 5 00000000 1G MUSK UND U 1 Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add support for FTLBsLeonid Yegoshin2014-01-227-14/+155
| | | | | | | | | | | | | | The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6139/
* MIPS: mm: Use the TLBINVF instruction to flush the VTLBLeonid Yegoshin2014-01-221-6/+12
| | | | | | | | | | | The TLBINVF instruction can be used to flush the entire VTLB. This eliminates the need for the TLBWI loop and improves performance. Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6138/
* MIPS: Add function for flushing the TLB using the TLBINV instructionLeonid Yegoshin2014-01-221-0/+13
| | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6136/
* MIPS: kernel: cpu-probe: Add support for probing proAptiv coresLeonid Yegoshin2014-01-221-0/+8
| | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6135/
* MIPS: Add support for the proAptiv coresLeonid Yegoshin2014-01-2210-1/+13
| | | | | | | | | | | | | | | | The proAptiv Multiprocessing System is a power efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The proAptiv Multiprocessing System combines a deep pipeline with multi-issue out of order execution for improved computational throughput. The proAptiv Multiprocessing System can contain one to six MIPS32r3 proAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6134/
* MIPS: Add processor identifiers for the proAptiv processorsLeonid Yegoshin2014-01-221-0/+2
| | | | | | | | | | Add processor identifiers for single core and multi-core proAptiv processors. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6133/
* MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLBLeonid Yegoshin2014-01-221-1/+3
| | | | | | | | | | | | For MIPS32R3 supported cores, the EHINV bit needs to be set when invalidating the TLB. This is necessary because the legacy software method of representing an invalid TLB entry using an unmapped address value is not guaranteed to work. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6132/
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