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path: root/drivers/clk/meson/meson8b.c
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* clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl2018-12-031-8/+731
* clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl2018-12-031-0/+5
* clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl2018-12-031-1/+1
* clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl2018-11-231-0/+244
* clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl2018-11-231-10/+10
* clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl2018-11-231-6/+6
* clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl2018-11-231-0/+63
* clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl2018-11-231-0/+5
* clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl2018-11-231-1/+2
* clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl2018-11-231-2/+9
* clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl2018-11-231-1/+1
* clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl2018-11-231-7/+8
* clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl2018-11-231-9/+15
* clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl2018-09-261-7/+6Star
* clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl2018-09-261-60/+34Star
* clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet2018-09-261-17/+17
* clk: meson: clk-pll: remove od parametersJerome Brunet2018-09-261-73/+78
* clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet2018-09-261-3/+0Star
* clk: meson: clk-pll: add enable bitJerome Brunet2018-09-261-0/+15
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-06-091-15/+62
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| * clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl2018-05-211-0/+7
| * clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-181-15/+1Star
| * clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl2018-05-151-0/+54
* | clk: meson: meson8b: fix meson8b_cpu_clk parent clock nameMartin Blumenstingl2018-04-251-1/+2
* | clk: meson: meson8b: fix meson8b_fclk_div3_div clock nameMartin Blumenstingl2018-04-251-1/+1
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* clk: meson: Drop unused local variable and add staticStephen Boyd2018-03-141-7/+6Star
* clk: meson: clean-up clk81 clocksJerome Brunet2018-03-131-4/+2Star
* clk: meson: add fdiv clock gatesJerome Brunet2018-03-131-10/+85
* clk: meson: add mpll pre-dividerJerome Brunet2018-03-131-3/+19
* clk: meson: add fractional part of meson8b fixed_pllJerome Brunet2018-03-131-0/+5
* clk: meson: rework meson8b cpu clockJerome Brunet2018-03-131-60/+113
* clk: meson: split divider and gate part of mpllJerome Brunet2018-03-131-21/+54
* clk: meson: migrate plls clocks to clk_regmapJerome Brunet2018-03-131-62/+87
* clk: meson: migrate mplls clocks to clk_regmapJerome Brunet2018-03-131-78/+77Star
* clk: meson: migrate muxes to clk_regmapJerome Brunet2018-03-131-18/+9Star
* clk: meson: migrate dividers to clk_regmapJerome Brunet2018-03-131-15/+8Star
* clk: meson: migrate gates to clk_regmapJerome Brunet2018-03-131-19/+20
* clk: meson: add regmap to the clock controllersJerome Brunet2018-03-131-1/+13
* clk: meson: remove obsolete commentsJerome Brunet2018-03-131-1/+0Star
* clk: meson: only one loop index is necessary in probeJerome Brunet2018-03-131-4/+4
* clk: meson: use devm_of_clk_add_hw_providerJerome Brunet2018-03-131-2/+2
* clk: meson: make the spinlock naming more specificYixun Lan2017-12-141-12/+12
* Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd2017-08-241-12/+148
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| * clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl2017-08-041-12/+147
| * clk: meson: meson8b: fix protection against undefined clksJerome Brunet2017-08-041-0/+1
* | clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet2017-08-011-0/+5
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* clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl2017-06-121-1/+4
* clk: meson: meson8b: mark clk81 as criticalMartin Blumenstingl2017-05-291-1/+1
* clk: meson8b: add the mplls clocks 0, 1 and 2Jerome Brunet2017-03-271-0/+103
* clk: meson8b: put dividers and muxes in tablesJerome Brunet2017-03-271-4/+18
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