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path: root/drivers/gpu/drm/i915/intel_pm.c
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* drm/i915: Change CHV SKU400 GPU freq divider to 10Ville Syrjälä2014-11-171-1/+2
* drm/i915: Add missing newline to 'DDR speed' debug messagesVille Syrjälä2014-11-171-2/+2
* drm/i915: Refactor vlv/chv GPU frequency divider setupVille Syrjälä2014-11-171-69/+35Star
* drm/i915: Improve PCBR debug informationVille Syrjälä2014-11-171-2/+6
* drm/i915: Warn if GPLL isn't used on vlv/chvVille Syrjälä2014-11-171-0/+6
* drm/i915: Add a name for the Punit GPLLENABLE bitVille Syrjälä2014-11-171-2/+2
* drm/i915: Silence valleyview_set_rps()Ville Syrjälä2014-11-171-7/+1Star
* drm/i915: Let's hope future platforms will use the same WM code as SKLDamien Lespiau2014-11-141-1/+1
* drm/i915: Clear PCODE_DATA1 on SNB+Damien Lespiau2014-11-141-2/+1Star
* drm/i915: Read the CCK fuse register from CCKVille Syrjälä2014-11-141-1/+4
* drm/i915: move rps irq enable/disable to i915_irq.cImre Deak2014-11-141-41/+0Star
* drm/i915: unify gen6/gen8 rps irq enable/disableImre Deak2014-11-141-38/+15Star
* drm/i915: unify gen6/gen8 pm irq helpersImre Deak2014-11-141-1/+1
* drm/i915/chv: Remove pre-production workaroundsArun Siluvery2014-11-141-12/+0Star
* drm/i915/skl: Enable Gen9 RC6Zhe Wang2014-11-071-1/+51
* drm/i915/skl: Log the order in which we flush the pipes in the WM codeDamien Lespiau2014-11-071-4/+7
* drm/i915/skl: Flush the WM configurationDamien Lespiau2014-11-071-0/+135
* drm/i915/skl: Stage the pipe DDB allocationDamien Lespiau2014-11-071-7/+7
* drm/i915/skl: Reduce the indentation level in skl_write_wm_values()Damien Lespiau2014-11-071-21/+21
* drm/i915/skl: Correctly align skl_compute_plane_wm() argumentsDamien Lespiau2014-11-071-5/+5
* drm/i915/skl: Rework when the transition WMs are computedDamien Lespiau2014-11-071-15/+31
* drm/i915/skl: Move all the WM compute functions in one placeDamien Lespiau2014-11-071-22/+22
* drm/i915/skl: Make res_blocks/lines intermediate values 32 bitsDamien Lespiau2014-11-071-16/+11Star
* drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm()Damien Lespiau2014-11-071-2/+2
* drm/i915/skl: Make 'end' of the DDB allocation entry exclusiveDamien Lespiau2014-11-071-9/+19
* drm/i915/skl: Check the DDB state at modesetDamien Lespiau2014-11-071-2/+2
* drm/i915/skl: Read back the DDB allocation hw stateDamien Lespiau2014-11-071-0/+29
* drm/i915/skl: Store the new WM state at the very end of the updateDamien Lespiau2014-11-071-2/+3
* drm/i915/gen9: Disable WM if corresponding latency is 0Vandana Kannan2014-11-071-2/+12
* drm/i915/gen9: Add 2us read latency to WM levelVandana Kannan2014-11-071-0/+16
* drm/i915/skl: Read the pipe WM HW statePradeep Bhat2014-11-071-0/+104
* drm/i915/skl: Program the DDB allocationDamien Lespiau2014-11-071-0/+9
* drm/i915/skl: Allocate DDB portions for display planesDamien Lespiau2014-11-071-0/+148
* drm/i915/skl: SKL Watermark ComputationPradeep Bhat2014-11-071-0/+422
* drm/i915/skl: Definition of SKL WM param structs for pipe/planePradeep Bhat2014-11-071-0/+8
* drm/i915/skl: Read the Memory Latency Values for WM computationPradeep Bhat2014-11-071-6/+70
* drm/i915/chv: Use 16 and 32 for low and high drain latency precision.Rodrigo Vivi2014-10-241-15/+25
* drm/i915/bdw: Remove BDW preproduction W/As until C stepping.Rodrigo Vivi2014-10-241-10/+0Star
* drm/i915: Do not export RC6p and RC6pp if they don't existRodrigo Vivi2014-10-241-5/+10
* Merge branch 'drm-intel-next-fixes' into drm-intel-nextDaniel Vetter2014-10-211-197/+46Star
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| * drm/i915: Don't spam dmesg with rps messages on vlv/chvVille Syrjälä2014-09-291-6/+7
| * Revert "drm/i915/bdw: BDW Software Turbo"Daniel Vetter2014-09-291-191/+39Star
* | drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/Daniel Vetter2014-10-031-1/+0Star
* | drm/i915: Extract intel_runtime_pm.cDaniel Vetter2014-10-011-1160/+0Star
* | Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter2014-09-301-2/+28
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| * | drm/i915/skl: Move gen9 pm initialization into its own branchDamien Lespiau2014-09-241-3/+3
| * | drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:sklDamien Lespiau2014-09-241-0/+8
| * | drm/i915/skl: Implement Wa4x4STCOptimizationDisable:sklDamien Lespiau2014-09-241-0/+4
| * | drm/i915/skl: Implement WaDisableSDEUnitClockGating:sklDamien Lespiau2014-09-241-0/+8
| * | drm/i915/skl: Restore pipe B/C interruptsSatheeshakrishna M2014-09-241-1/+1
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