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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
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* drm/i915: Refactor VLV display power well init/deinitVille Syrjälä2015-07-131-29/+23Star
* drm/i915: Simplify CHV pipe A power well codeVille Syrjälä2015-07-131-27/+20Star
* drm/i915: Apply OCD to VLV/CHV DPLL definesVille Syrjälä2015-07-131-4/+4
* drm/i915: Keep GMCH DPLL VGA mode always disabledVille Syrjälä2015-07-131-4/+4
* drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä2015-05-281-94/+4Star
* drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä2015-05-281-0/+2
* drm/i915: Fix typo in intel_runtime_pm.cMasanari Iida2015-05-201-2/+2
* Revert "drm/i915: Hack to tie both common lanes together on chv"Ville Syrjälä2015-05-081-12/+2Star
* drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHVVille Syrjälä2015-05-081-5/+31
* drm/i915/skl: Make the Misc I/O power well part of the PLLS domainDamien Lespiau2015-05-081-0/+1
* drm/i915/skl: Add the INIT power domain to the MISC I/O power wellDamien Lespiau2015-05-081-1/+2
* drm/i915/skl: Assert the requirements to enter or exit DC6.Suketu Shah2015-05-081-4/+36
* Implement enable/disable for Display C6 stateA.Sunil Kamath2015-05-081-2/+25
* drm/i915/skl: Add DC6 Trigger sequence.Suketu Shah2015-05-081-7/+36
* drm/i915/skl: Assert the requirements to enter or exit DC5.Suketu Shah2015-05-081-5/+46
* drm/i915/skl: Implement enable/disable for Display C5 state.A.Sunil Kamath2015-05-081-2/+39
* drm/i915/skl: Add DC5 Trigger SequenceSuketu Shah2015-05-081-0/+33
* drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath2015-04-161-0/+66
* drm/i915/bxt: Define BXT power domainsSatheeshakrishna M2015-04-141-0/+55
* drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven2015-03-171-3/+3
* drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau2015-03-171-1/+3
* drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau2015-03-171-1/+1
* drm/i915/skl: Restore pipe interrupt registers after power well enablingDamien Lespiau2015-03-171-0/+31
* drm/i915/skl: Mirror what we do on HSW for the power well enable log messageDamien Lespiau2015-03-171-1/+1
* drm/i915/skl: Introduce enable_requested and is_enabled in the power well codeDamien Lespiau2015-03-171-4/+6
* drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe maskDamien Lespiau2015-03-171-1/+2
* drm/i915/skl: Implementation of SKL display power well supportSatheeshakrishna M2015-02-131-0/+220
* drm/i915/skl: Adding power domains for AUX controllersSatheeshakrishna M2015-01-271-0/+15
* Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queuedDaniel Vetter2015-01-121-83/+0Star
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| * drm/i915: remove unused power_well/get_cdclk_freq apiImre Deak2015-01-121-56/+0Star
| * drm/i915: Kill check_power_well() callsVille Syrjälä2014-12-181-27/+0Star
* | drm/i915: tame the chattermouth (v2)Rob Clark2014-12-161-1/+1
* | drm/i915: Fix short description of intel_display_power_is_enabled()Damien Lespiau2014-12-031-1/+1
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* drm/i915: Reinit display irqs and hpd from chv pipe-a power wellVille Syrjälä2014-11-171-0/+23
* drm/i915: Enable pipe-a power well on chvVille Syrjälä2014-11-041-1/+12
* drm/i915: Do vlv cmnlane toggle w/a in more casesVille Syrjälä2014-11-041-5/+2Star
* drm/i915: only run hsw_power_well_post_enable when really neededPaulo Zanoni2014-10-241-1/+1
* drm/i915: Use dev_priv instead of dev in irq setup functionsDaniel Vetter2014-10-031-1/+1
* drm/i915: Kerneldoc for intel_runtime_pm.cDaniel Vetter2014-10-011-1/+165
* drm/i915: Call runtime_pm_disable directlyDaniel Vetter2014-10-011-16/+18
* drm/i915: Move intel_display_set_init_power to intel_runtime_pm.cDaniel Vetter2014-10-011-0/+14
* drm/i915: Bikeshed rpm functions name a bit.Daniel Vetter2014-10-011-8/+13
* drm/i915: Extract intel_runtime_pm.cDaniel Vetter2014-10-011-0/+1190
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