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path:
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/
drivers
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gpu
/
drm
/
i915
/
intel_runtime_pm.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
drm/i915: Skip CHV PHY asserts until PHY has been fully reset
Ville Syrjälä
2015-10-06
1
-1
/
+45
*
drm/i915: fixup runtime PM handling v2
Jesse Barnes
2015-09-30
1
-3
/
+0
*
drm/i915/skl: Block disable call for pw1 if dmc firmware is present.
Animesh Manna
2015-09-30
1
-3
/
+9
*
drm/i915: make CSR firmware messages less verbose
Jesse Barnes
2015-09-14
1
-18
/
+18
*
Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
Daniel Vetter
2015-09-02
1
-0
/
+2
|
\
|
*
drm/i915/skl: Adding DDI_E power well domain
Xiong Zhang
2015-08-31
1
-0
/
+2
*
|
drm/i915: Add CHV PHY LDO power sanity checks
Ville Syrjälä
2015-09-01
1
-17
/
+109
*
|
drm/i915: Add some CHV DPIO lane power state asserts
Ville Syrjälä
2015-09-01
1
-0
/
+54
*
|
drm/i915: Force CL2 off in CHV x1 PHY
Ville Syrjälä
2015-08-26
1
-0
/
+9
*
|
drm/i915: Enable DPIO SUS clock gating on CHV
Ville Syrjälä
2015-08-26
1
-1
/
+2
*
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Ville Syrjälä
2015-08-26
1
-0
/
+29
*
|
drm/i915: Implement PHY lane power gating for CHV
Ville Syrjälä
2015-08-26
1
-9
/
+114
*
|
drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
Ville Syrjälä
2015-08-26
1
-21
/
+24
*
|
drm/i915: Add locking around chv_phy_control_init()
Ville Syrjälä
2015-08-26
1
-0
/
+2
|
/
*
drm/i915: Extract a intel_power_well_disable() function
Damien Lespiau
2015-08-05
1
-5
/
+10
*
drm/i915: Extract a intel_power_well_enable() function
Damien Lespiau
2015-08-05
1
-5
/
+10
*
drm/i915: Refactor VLV display power well init/deinit
Ville Syrjälä
2015-07-13
1
-29
/
+23
*
drm/i915: Simplify CHV pipe A power well code
Ville Syrjälä
2015-07-13
1
-27
/
+20
*
drm/i915: Apply OCD to VLV/CHV DPLL defines
Ville Syrjälä
2015-07-13
1
-4
/
+4
*
drm/i915: Keep GMCH DPLL VGA mode always disabled
Ville Syrjälä
2015-07-13
1
-4
/
+4
*
drm/i915: Throw out WIP CHV power well definitions
Ville Syrjälä
2015-05-28
1
-94
/
+4
*
drm/i915: Use the default 600ns LDO programming sequence delay
Ville Syrjälä
2015-05-28
1
-0
/
+2
*
drm/i915: Fix typo in intel_runtime_pm.c
Masanari Iida
2015-05-20
1
-2
/
+2
*
Revert "drm/i915: Hack to tie both common lanes together on chv"
Ville Syrjälä
2015-05-08
1
-12
/
+2
*
drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
Ville Syrjälä
2015-05-08
1
-5
/
+31
*
drm/i915/skl: Make the Misc I/O power well part of the PLLS domain
Damien Lespiau
2015-05-08
1
-0
/
+1
*
drm/i915/skl: Add the INIT power domain to the MISC I/O power well
Damien Lespiau
2015-05-08
1
-1
/
+2
*
drm/i915/skl: Assert the requirements to enter or exit DC6.
Suketu Shah
2015-05-08
1
-4
/
+36
*
Implement enable/disable for Display C6 state
A.Sunil Kamath
2015-05-08
1
-2
/
+25
*
drm/i915/skl: Add DC6 Trigger sequence.
Suketu Shah
2015-05-08
1
-7
/
+36
*
drm/i915/skl: Assert the requirements to enter or exit DC5.
Suketu Shah
2015-05-08
1
-5
/
+46
*
drm/i915/skl: Implement enable/disable for Display C5 state.
A.Sunil Kamath
2015-05-08
1
-2
/
+39
*
drm/i915/skl: Add DC5 Trigger Sequence
Suketu Shah
2015-05-08
1
-0
/
+33
*
drm/i915/bxt: Implement enable/disable for Display C9 state
A.Sunil Kamath
2015-04-16
1
-0
/
+66
*
drm/i915/bxt: Define BXT power domains
Satheeshakrishna M
2015-04-14
1
-0
/
+55
*
drm/i915: Spelling s/auxilliary/auxiliary/
Geert Uytterhoeven
2015-03-17
1
-3
/
+3
*
drm/i915/skl: Restore the DDI translation tables when enabling PW1
Damien Lespiau
2015-03-17
1
-1
/
+3
*
drm/i915: Remove unused condition in hsw_power_well_post_enable()
Damien Lespiau
2015-03-17
1
-1
/
+1
*
drm/i915/skl: Restore pipe interrupt registers after power well enabling
Damien Lespiau
2015-03-17
1
-0
/
+31
*
drm/i915/skl: Mirror what we do on HSW for the power well enable log message
Damien Lespiau
2015-03-17
1
-1
/
+1
*
drm/i915/skl: Introduce enable_requested and is_enabled in the power well code
Damien Lespiau
2015-03-17
1
-4
/
+6
*
drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
Damien Lespiau
2015-03-17
1
-1
/
+2
*
drm/i915/skl: Implementation of SKL display power well support
Satheeshakrishna M
2015-02-13
1
-0
/
+220
*
drm/i915/skl: Adding power domains for AUX controllers
Satheeshakrishna M
2015-01-27
1
-0
/
+15
*
Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queued
Daniel Vetter
2015-01-12
1
-83
/
+0
|
\
|
*
drm/i915: remove unused power_well/get_cdclk_freq api
Imre Deak
2015-01-12
1
-56
/
+0
|
*
drm/i915: Kill check_power_well() calls
Ville Syrjälä
2014-12-18
1
-27
/
+0
*
|
drm/i915: tame the chattermouth (v2)
Rob Clark
2014-12-16
1
-1
/
+1
*
|
drm/i915: Fix short description of intel_display_power_is_enabled()
Damien Lespiau
2014-12-03
1
-1
/
+1
|
/
*
drm/i915: Reinit display irqs and hpd from chv pipe-a power well
Ville Syrjälä
2014-11-17
1
-0
/
+23
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