summaryrefslogtreecommitdiffstats
path: root/drivers/mtd/nand/pxa3xx_nand.c
Commit message (Collapse)AuthorAgeFilesLines
* mtd: nand: remove deprecated pxa3xx_nand driverMiquel Raynal2018-02-231-2105/+0Star
| | | | | | | | | | All board files and defconfig files have been moved to use the new marvell_nand driver instead of pxa3xx_nand, so we can safely remove this file now. People should use the new driver which is supposed to behave exactly like the old one. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
* Merge tag 'mtd/for-4.16' of git://git.infradead.org/linux-mtdLinus Torvalds2018-01-291-8/+6Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD updates from Boris Brezillon: "MTD core changes: - Rework core functions to avoid duplicating generic checks in NAND/OneNAND sub-layers - Update the MAINTAINERS entry to reflect the fact that MTD maintainers now use a single git tree MTD driver changes: - CFI: use macros instead of inline functions to limit stack usage and make KASAN happy NAND core changes: - Fix NAND_CMD_NONE handling in nand_command[_lp]() hooks - Introduce the ->exec_op() infrastructure - Rework NAND buffers handling - Fix ECC requirements for K9F4G08U0D - Fix nand_do_read_oob() to return the number of bitflips - Mark K9F1G08U0E as not supporting subpage writes NAND driver changes: - MTK: Rework the driver to support new IP versions - OMAP OneNAND: Full rework to use new APIs (libgpio, dmaengine) and fix DT support - Marvell: Add a new driver to replace the pxa3xx one SPI NOR core changes: - Add support to new ISSI and Cypress/Spansion memory parts. - Fix support of Micron memories by checking error bits in the FSR. - Fix update of block-protection bits by reading back the SR. - Restore the internal state of the SPI flash memory when removing the device. SPI NOR driver changes: - Maintenance for Freescale, Intel and Metiatek drivers. - Add support of the direct access mode for the Cadence QSPI controller" * tag 'mtd/for-4.16' of git://git.infradead.org/linux-mtd: (93 commits) mtd: nand: sunxi: Fix ECC strength choice mtd: nand: gpmi: Fix subpage reads mtd: nand: Fix build issues due to an anonymous union mtd: nand: marvell: Fix missing memory allocation modifier mtd: nand: marvell: remove redundant variable 'oob_len' mtd: nand: marvell: fix spelling mistake: "suceed"-> "succeed" mtd: onenand: omap2: Remove redundant dev_err call in omap2_onenand_probe() mtd: Remove duplicate checks on mtd_oob_ops parameter mtd: Fallback to ->_read/write_oob() when ->_read/write() is missing mtd: mtdpart: Make ECC stat handling consistent mtd: onenand: omap2: print resource using %pR format string mtd: mtk-nor: modify functions' name more generally mtd: onenand: samsung: remove incorrect __iomem annotation MAINTAINERS: Add entry for Marvell NAND controller driver ARM: OMAP2+: Remove gpmc-onenand mtd: onenand: omap2: Configure driver from DT mtd: onenand: omap2: Decouple DMA enabling from INT pin availability mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific mtd: onenand: omap2: Convert to use dmaengine for memcpy mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation ...
| * mtd: nand: force drivers to explicitly send READ/PROG commandsBoris Brezillon2017-12-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core currently send the READ0 and SEQIN+PAGEPROG commands in nand_do_read/write_ops(). This is inconsistent with ->read/write_oob[_raw]() hooks behavior which are expected to send these commands. There's already a flag (NAND_ECC_CUSTOM_PAGE_ACCESS) to inform the core that a specific controller wants to send the READ/SEQIN+PAGEPROG commands on its own, but it's an opt-in flag, and existing drivers are unlikely to be updated to pass it. Moreover, some controllers cannot dissociate the READ/PAGEPROG commands from the associated data transfer and ECC engine activation, and developers have to hack things in their ->cmdfunc() implementation to handle such complex cases, or have to accept the perf penalty of sending twice the same command. To address this problem we are planning on adding a new interface which is passed all information about a NAND operation (including the amount of data to transfer) and replacing all calls to ->cmdfunc() to calls to this new ->exec_op() hook. But, in order to do that, we need to have all ->cmdfunc() calls placed near their associated ->read/write_buf/byte() calls. Modify the core and relevant drivers to make NAND_ECC_CUSTOM_PAGE_ACCESS the default case, and remove this flag. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [miquel.raynal@free-electrons.com: tested, fixed and rebased on nand/next] Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * mtd: nand: provide several helpers to do common NAND operationsBoris Brezillon2017-12-141-5/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is part of the process of removing direct calls to ->cmdfunc() outside of the core in order to introduce a better interface to execute NAND operations. Here we provide several helpers and make use of them to remove all direct calls to ->cmdfunc(). This way, we can easily modify those helpers to make use of the new ->exec_op() interface when available. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [miquel.raynal@free-electrons.com: rebased and fixed some conflicts] Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: nand: pxa3xx: Fix READOOB implementationBoris Brezillon2018-01-061-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | In the current driver, OOB bytes are accessed in raw mode, and when a page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the driver must read the whole spare area (64 bytes in case of a 2k page, 16 bytes for a 512 page). The driver was only reading the free OOB bytes, which was leaving some unread data in the FIFO and was somehow leading to a timeout. We could patch the driver to read ->spare_size + ->ecc_size instead of just ->spare_size when READOOB is requested, but we'd better make in-band and OOB accesses consistent. Since the driver is always accessing in-band data in non-raw mode (with the ECC engine enabled), we should also access OOB data in this mode. That's particularly useful when using the BCH engine because in this mode the free OOB bytes are also ECC protected. Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support") Cc: stable@vger.kernel.org Reported-by: Sean Nyekjær <sean.nyekjaer@prevas.dk> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Richard Weinberger <richard@nod.at>
* mtd: nand: pxa3xx: enable NAND controller if the SoC needs itMiquel Raynal2017-10-071-4/+37
| | | | | | | | | | | | Marvell recent SoCs like A7k/A8k do not boot with NAND flash controller activated by default. Enabling the controller is a matter of writing in a system controller register that may also be used for other NAND related choices. This change is needed to stay bootloader independent. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: nand: Rename nand.h into rawnand.hBoris Brezillon2017-08-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | We are planning to share more code between different NAND based devices (SPI NAND, OneNAND and raw NANDs), but before doing that we need to move the existing include/linux/mtd/nand.h file into include/linux/mtd/rawnand.h so we can later create a nand.h header containing all common structure and function prototypes. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Peter Pan <peterpandong@micron.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Acked-by: Wenyou Yang <wenyou.yang@microchip.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Han Xu <han.xu@nxp.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-By: Harvey Hunt <harveyhuntnexus@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Krzysztof Halasa <khalasa@piap.pl>
* mtd: nand: Make sure drivers not supporting SET/GET_FEATURES return -ENOTSUPPBoris Brezillon2017-05-301-0/+2
| | | | | | | | | | | | | | | | A lot of drivers are providing their own ->cmdfunc(), and most of the time this implementation does not support all possible NAND operations. But since ->cmdfunc() cannot return an error code, the core has no way to know that the operation it requested is not supported. This is a problem we cannot address for all kind of operations with the current design, but we can prevent these silent failures for the GET/SET FEATURES operation by overloading the default ->onfi_{set,get}_features() methods with one returning -ENOTSUPP. Reported-by: Chris Packham <Chris.Packham@alliedtelesis.co.nz> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
* mtd: nand: pxa3xx: return error code of nand_scan_ident() on errorMasahiro Yamada2016-11-071-2/+3
| | | | | | | | | | The nand_scan_ident() returns an appropriate error value when it fails. Use it instead of the fixed error code -ENODEV. (This driver is already doing so for nand_scan_tail().) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: nand: pxa3xx_nand: write exactly one message on probe failureUwe Kleine-König2016-11-071-7/+10
| | | | | | | | | | | For some error paths alloc_nand_resource() emitted an error message, for others it didn't. Make it consistently print a message including the error code where it's not constant and drop the hardly helpful additional message printed by the caller of alloc_nand_resource. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: nand: import nand_hw_control_init()Marc Gonzalez2016-09-231-2/+1Star
| | | | | | | | The code to initialize a struct nand_hw_control is duplicated across several drivers. Factorize it using an inline function. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: nand: pxa3xx: switch to mtd_ooblayout_opsBoris Brezillon2016-05-051-40/+64
| | | | | | | Implementing the mtd_ooblayout_ops interface is the new way of exposing ECC/OOB layout to MTD users. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: nand: pxa3xx: rely on generic DT parsing done in nand_scan_ident()Boris Brezillon2016-04-191-17/+11Star
| | | | | | | | | | The core now takes care of parsing generic DT properties in nand_scan_ident() when nand_set_flash_node() has been called. Rely on this initialization instead of calling of_get_nand_xxx() manually. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* mtd: nand: pxa3xx_nand: kill unused field 'drcmr_cmd'Brian Norris2016-03-071-10/+0Star
| | | | | | | | | With this removal, we don't need to 'get' the second DMA resource either, as it's also unused. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx_nand: fix dmaengine initializationRobert Jarzmik2016-03-051-1/+1
| | | | | | | | | | | | | | | | | | When the driver is initialized in a pure device-tree platform, the driver's probe fails allocating the dma channel : [ 525.624435] pxa3xx-nand 43100000.nand: no resource defined for data DMA [ 525.632088] pxa3xx-nand 43100000.nand: alloc nand resource failed The reason is that the DMA IO resource is not acquired through platform resources but by OF bindings. Fix this by ensuring that DMA IO resources are only queried in the non device-tree case. Fixes: 8f5ba31aa565 ("mtd: nand: pxa3xx-nand: switch to dmaengine") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx_nand: add support for partial chunksThomas Petazzoni2016-02-121-56/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is needed to properly support the 8-bits ECC configuration with 4KB pages. When pages larger than 2 KB are used on platforms using the PXA3xx NAND controller, the reading/programming operations need to be split in chunks of 2 KBs or less because the controller FIFO is limited to about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to this requirement, the data layout on NAND is a bit strange, with ECC interleaved with data, at the end of each chunk. When a 4-bits ECC configuration is used with 4 KB pages, the physical data layout on the NAND looks like this: | 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC | So the data chunks have an equal size, 2080 bytes for each chunk, which the driver supports properly. When a 8-bits ECC configuration is used with 4KB pages, the physical data layout on the NAND looks like this: | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC | So, the spare area is stored in its own chunk, which has a different size than the other chunks. Since OOB is not used by UBIFS, the initial implementation of the driver has chosen to not support reading this additional "spare" chunk of data. Unfortunately, Marvell has chosen to store the BBT signature in the OOB area. Therefore, if the driver doesn't read this spare area, Linux has no way of finding the BBT. It thinks there is no BBT, and rewrites one, which U-Boot does not recognize, causing compatibility problems between the bootloader and the kernel in terms of NAND usage. To fix this, this commit implements the support for reading a partial last chunk. This support is currently only useful for the case of 8 bits ECC with 4 KB pages, but it will be useful in the future to enable other configurations such as 12 bits and 16 bits ECC with 4 KB pages, or 8 bits ECC with 8 KB pages, etc. All those configurations have a "last" chunk that doesn't have the same size as the other chunks. In order to implement reading of the last chunk, this commit: - Adds a number of new fields to the pxa3xx_nand_info to describe how many full chunks and how many chunks we have, the size of full chunks and partial chunks, both in terms of data area and spare area. - Fills in the step_chunk_size and step_spare_size variables to describe how much data and spare should be read/written for the current read/program step. - Reworks the state machine to accommodate doing the additional read or program step when a last partial chunk is used. This commit has been tested on a Marvell Armada 398 DB board, with a 4KB page NAND, tested in both 4 bits ECC and 8 bits ECC configurations. Robert Jarzmik has tested on some PXA platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx_nand: add register access debugRobert Jarzmik2016-02-011-5/+17
| | | | | | | | | Add verbose debug for register accesses. This enables easier debugging by following where and how hardware is stimulated, and how it answers. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: make use of nand_set/get_controller_data() helpersBoris BREZILLON2016-01-071-11/+11
| | | | | | | | | New helpers have been added to avoid directly accessing chip->field. Use them where appropriate. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Brian: fixed a few rebase conflicts] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: remove useless mtd->priv = chip assignmentsBoris BREZILLON2015-12-181-1/+0Star
| | | | | | | | | mtd_to_nand() now uses the container_of() approach to transform an mtd_info pointer into a nand_chip one. Drop useless mtd->priv assignments from NAND controller drivers. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx: use the mtd instance embedded in struct nand_chipBoris BREZILLON2015-12-181-16/+17
| | | | | | | struct nand_chip now embeds an mtd device. Make use of this mtd instance. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: make use of mtd_to_nand() in NAND driversBoris BREZILLON2015-12-081-9/+9
| | | | | | | | mtd_to_nand() was recently introduced to avoid direct accesses to the mtd->priv field. Update all NAND drivers to use it. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: fix drivers abusing mtd->privBoris BREZILLON2015-11-191-11/+19
| | | | | | | | | | | | | The ->priv field of the mtd_info object attached to a nand_chip device should point to the nand_chip device. The pxa and cafe drivers are assigning this field their own private structure, which works fine as long as the nand_chip field is the first one in the driver private struct but seems a bit fragile. Fix that by setting mtd->priv to point the nand_chip field and assigning chip->priv to the private structure head. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: Gate/ungate the NAND clock in suspend/resume pathsEzequiel García2015-11-171-0/+6
| | | | | | | | The NAND clock can be disabled on suspend and enabled on resume. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: Remove dead codeEzequiel García2015-11-171-5/+0Star
| | | | | | | | | This macro is not used anymore, so it's just dead code. Remove it. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: Remove redundant NAND sensingEzequiel García2015-11-171-33/+8Star
| | | | | | | | | | | | | Currently, the driver is trying to detect the presence of a chip by issuing a RESET command before nand_scan_ident. This seems completely redundant, and is also a layering violation as nand_scan_ident is in charge of device detection. This commit removes the RESET command use, and moves the initial timing configuration to pxa3xx_nand_config_ident. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: Simplify pxa3xx_nand_scanEzequiel García2015-11-161-16/+14Star
| | | | | | | | | This commit simplifies the initial configuration performed by pxa3xx_nand_scan. No functionality change is intended. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: Fix initial controller configurationEzequiel García2015-11-161-13/+22
| | | | | | | | | | | | | | | | The Data Flash Control Register (NDCR) contains two types of parameters: those that are needed for device identification, and those that can only be set after device identification. Therefore, the driver can't set them all at once and instead needs to configure the first group before nand_scan_ident() and the second group later. Let's split pxa3xx_nand_config in two halves, and set the parameters that depend on the device geometry once this is known. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: Increase the initial chunk sizeEzequiel García2015-11-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The chunk size represents the size of the data chunks, which is used by the controllers that allow to split transfered data. However, the initial chunk size is used in a non-splitted way, during device identification. Therefore, it must be large enough for all the NAND commands issued during device identification. This includes NAND_CMD_PARAM which was recently changed to transfer up to 2048 bytes (for the redundant parameter pages). Thus, the initial chunk size should be 2048 as well. On Armada 370/XP platforms (NFCv2) booted without the keep-config devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM command: [..] pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device pxa3xx-nand f10d0000.nand: Wait time out!!! nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38 nand: Micron MT29F8G08ABABAWP nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224 Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: drop unnecessary partition parser dataBrian Norris2015-11-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | All of these drivers set up a parser data struct just to communicate DT partition data. This field has been deprecated and is instead supported by telling nand_scan_ident() about the 'flash_node'. This patch: * sets chip->flash_node for those drivers that didn't already (but used OF partitioning) * drops the parser data * switches to the simpler mtd_device_register() where possible, now that we've eliminated one of the auxiliary parameters Now that we've assigned chip->flash_node for these drivers, we can probably rely on nand_dt_init() to do more of the DT parsing for us, but for now, I don't want to fiddle with each of these drivers. The parsing is done in duplicate for now on some drivers. I don't think this should break things. (Famous last words.) (Rolled in some changes by Boris Brezillon) Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: pxa3xx_nand: clean up the pxa3xx timingsAntoine Ténart2015-10-261-17/+8Star
| | | | | | | | | With the previous modifications, lots of pxa3xx specific definitions can be removed. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: rework flash detection and timing setupAntoine Ténart2015-10-261-88/+35Star
| | | | | | | | | | Rework the pxa3xx_nand driver to allow using functions exported by the nand framework to detect the flash and the timings. Then setup the timings using the helpers previously added. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: add helpers to setup the timingsAntoine Ténart2015-10-261-0/+122
| | | | | | | | | | Add helpers to setup the timings in the pxa3xx driver. These helpers allow to either make use of the nand framework nand_sdr_timings or the pxa3xx specific pxa3xx_nand_host, for compatibility reasons. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: fix some compile issues on non-ARM archesAntoine Ténart2015-10-261-2/+2
| | | | | | | | | | | Using readsl() result in a build error on i386. Fix this by using ioread32_rep() instead, to allow compile testing the pxa3xx nand driver on other architectures later. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: switch to device PMBrian Norris2015-10-191-7/+11
| | | | | | | | The old PM model is deprecated. This is equivalent. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* mtd: pxa3xx_nand: don't duplicate MTD suspend/resumeBrian Norris2015-10-191-17/+0Star
| | | | | | | | | | | | | mtd_{suspend,resume}() get called from mtdcore in a class suspend/resume callback. We don't need to call them again here. In practice, this would actually work OK, as nand_base actually handles nesting OK -- it just might print warnings. Untested, but there are few (no?) users of PM for this driver AFAIK. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* mtd: nand: pass page number to ecc->write_xxx() methodsBoris BREZILLON2015-10-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ->read_xxx() methods are all passed the page number the NAND controller is supposed to read, but ->write_xxx() do not have such a parameter. This is a problem if we want to properly implement data scrambling/randomization in order to mitigate MLC sensibility to repeated pattern: to prevent bitflips in adjacent pages in the same block we need to avoid repeating the same pattern at the same offset in those pages, hence the randomizer/scrambler engine need to be passed the page value in order to adapt its seed accordingly. Moreover, adding the page parameter to the ->write_xxx() methods add some consistency to the current API. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Josh Wu <josh.wu@atmel.com> CC: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> CC: Maxime Ripard <maxime.ripard@free-electrons.com> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org> CC: Huang Shijie <shijie.huang@arm.com> CC: Stefan Agner <stefan@agner.ch> CC: devel@driverdev.osuosl.org CC: linux-arm-kernel@lists.infradead.org CC: linux-kernel@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx_nand: show parent device in sysfsFrans Klaver2015-10-131-1/+1
| | | | | | | | | Fix a bug where parent device symlinks aren't shown in sysfs. While at it, make use of the default owner value set by mtdcore. Signed-off-by: Frans Klaver <fransklaver@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx-nand: prevent DFI bus lockup on removalRobert Jarzmik2015-09-291-2/+15
| | | | | | | | | | | | | | | | | | | | | After the conversion of pxa architecture to common clock framework, the NAND clock can be disabled on driver exit. In this case, it happens that if the driver used the NAND and set the DFI arbitration bit, the next access to a static memory controller area, such as an ethernet card, will stall the system bus, and the core will be stalled forever. This is especially true on pxa31x SoCs, where the NDCR was augmented with a new bit to prevent this lockups by giving full ownership of the DFI arbiter to the SMC, in change SCr#6. Fix this by clearing the DFI arbritration bit in driver exit. This effectively prevents a lockup on zylonite when removing pxa3xx-nand module, and using ethernet afterwards. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx-nand: switch to dmaengineRobert Jarzmik2015-09-281-114/+108Star
| | | | | | | | | | | | | | | | | Now pxa architecture has a dmaengine driver, remove the access to direct dma registers in favor of the more generic dmaengine code. This should be also applicable for mmp and orion, provided they work in device-tree environment. This patch also removes the previous hack which was necessary to make the driver work in a devicetree environment. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> [Brian: fixup use of 'enum dma_transfer_direction'] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: Remove unused platform-data flash specificationEzequiel García2015-09-021-6/+27
| | | | | | | | | | | | | | | | The driver supports board files specificating the flash device, by passing a pxa3xx_nand_flash struct (with flash parameters) in the platform data struct. Currently this support is not being used by any board file. Moreover, we'd like to deprecate such usage in favor of using the device table in nand_ids.c. So let's remove the ad-hoc flash specification. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* nand: pxa3xx: Increase READ_ID buffer and make the size staticEzequiel García2015-08-201-21/+10Star
| | | | | | | | | | | The read ID count should be made as large as the maximum READ_ID size, so there's no need to have dynamic size. This commit sets the hardware maximum read ID count, which should be more than enough on all cases. Also, we get rid of the read_id_bytes, and use a macro instead. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx-nand: fix random command timeoutsRobert Jarzmik2015-08-201-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When 2 commands are submitted in a row, and the second is very quick, the completion of the second command might never come. This happens especially if the second command is quick, such as a status read after an erase. The issue is that in the interrupt handler, the status bits are cleared after the new command is issued. There is a small temporal window where this happens : - the previous command has set the command done bit - the ready for a command bit is set - the handler submits the next command - just then, the command completes, and the command done bit is still set - the handler clears the "previous" command done bit - the handler exits In this flow, the "command done" of the next command will never trigger a new interrupt to finish the status command, as it was cleared for both commands. Fix this by clearing the status bit before submitting a new command. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx_nand: fix early spurious interruptRobert Jarzmik2015-08-201-1/+1
| | | | | | | | | | | | | | | | | When the nand is first probe, and upon the first command start, the status bits should be cleared before the interrupts are unmasked. The bug is tricky : if the bootloader left a status bit set, the unmasking of interrupts does trigger the interrupt handler before the first command is issued, blocking the good behavior of the nand. The same would happen if in pxa3xx_nand code flow a status bit is left, and then a command is started. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: add a default chunk sizeAntoine Ténart2015-08-191-0/+3
| | | | | | | | | | | | | | | | | When keeping the configuration set by the bootloader (by using the marvell,nand-keep-config property), the pxa3xx_nand_detect_config() function is called and set the chunk size to 512 as a default value if NDCR_PAGE_SZ is not set. In the other case, when not keeping the bootloader configuration, no chunk size is set. Fix this by adding a default chunk size of 512. Fixes: 70ed85232a93 ("mtd: nand: pxa3xx: Introduce multiple page I/O support") Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Robert Jarzmik <robert.jarzmik@free> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* nand: pxa3xx: Increase initial buffer sizeEzequiel Garcia2015-08-141-6/+9
| | | | | | | | | | | | | The initial buffer is used for the initial commands used to detect a flash device (STATUS, READID and PARAM). ONFI param page is 256 bytes, and there are three redundant copies to be read. JEDEC param page is 512 bytes, and there are also three redundant copies to be read. Hence this buffer should be at least 512 x 3. This commits rounds the buffer size to 2048. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx: fix build on ARM64Rob Herring2015-05-071-11/+10Star
| | | | | | | | | | | | | | | | | | | In preparation to enable ARCH_MMP on ARM64, a couple of fixes are needed to build the pxa3xx_nand driver: Legacy DMA will only used on ARM, so also make it condtional on CONFIG_ARM. __raw_{read,write}sl are not available on ARM64 or generically, so use the readsl/writesl variants instead. Somewhat inconsistently, {read,write}sl are inherently non-swapping with the generic version using __raw_{read,write}l. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mtd@lists.infradead.org [Brian: added one more __raw_readsl -> readsl] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: pxa3xx: Switch FIFO draining to jiffies-based timeoutMaxime Ripard2015-05-071-11/+9Star
| | | | | | | | Now that the driver handles the FIFO draining in a threaded interrupt, we can base our timeout on jiffies and sleeping, instead of using mdelay. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: cleanup wait_for_completion handlingNicholas Mc Guire2015-03-311-14/+10Star
| | | | | | | | | | | | | | | | | | | | | return type of wait_for_completion_timeout is unsigned long not int, this patch uses the return value of wait_for_completion_timeout in the condition directly rather than assigning it to an incorrect type variable. The variable used for handling the return of wait_for_cmpletion_timeout was int but should be unsigned long, where it was not in use for anything else and the return value in case of completion (>0) is not used it was removed and wait_for_completion_timeout() used directly in the if condition. To make the timeout values a bit simpler to read and also handle all of the corner cases correctly the declarations are moved to msecs_to_jiffies(). The timeout declaration cleanup is just for readability Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: pxa3xx_nand: initialiaze pxa3xx_flash_ids to 0Antoine Ténart2015-02-281-0/+2
| | | | | | | | | pxa3xx_flash_ids wasn't initialized to 0, which in certain cases could end up containing corrupted values in its members. Fix this to avoid possible issues. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* Merge MTD updates into -nextBrian Norris2015-02-281-0/+2
|\
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-21 19:25:13 +0200