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* Merge tag 'v5.2-rc4' into spi-5.3Mark Brown2019-06-101-12/+1Star
|\ | | | | | | Linux 5.2-rc4
| * treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | spi: tegra114: set master cleanup and also invoke it on probe errorSowjanya Komatineni2019-05-231-0/+3
| | | | | | | | | | | | | | | | This patch sets master cleanup and also invokes tegra spi clean on tegra spi probe failure to release tegra spi client data. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: add support for TX and RX trimmersSowjanya Komatineni2019-05-151-2/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra SPI master controller has programmable trimmers to adjust the data with respect to the clock. These trimmers are programmed in TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY fields of COMMAND2 register. SPI TX trimmer is to adjust the outgoing data with respect to the outgoing clock and SPI RX trimmer is to adjust the loopback clock with respect to the incoming data from the slave device. These trimmers vary based on trace lengths of the platform design for each of the slaves on the SPI bus and optimal value programmed is from the platform validation across PVT. This patch adds support for configuring TX and RX clock delay trimmers through the device tree properties. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: add support for HW CS timingSowjanya Komatineni2019-05-151-2/+46
| | | | | | | | | | | | | | | | This patch implements set_cs_timing SPI controller method to allow SPI client driver to configure device specific SPI CS timings. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: add support for hw based csSowjanya Komatineni2019-05-151-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra SPI controller supports both HW and SW based CS control for SPI transfers. This patch adds support for HW based CS control where CS is driven to active state during the transfer and is driven inactive at the end of the transfer directly by the HW. This patch enables the use of HW based CS only for single transfers without cs_change request. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: add support for gpio based CSSowjanya Komatineni2019-05-151-0/+13
|/ | | | | | | | This patch adds support for GPIO based CS control through SPI core function spi_set_cs. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge branch 'spi-5.2' into spi-nextMark Brown2019-05-021-7/+90
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| * spi: tegra114: add support for interrupt maskSowjanya Komatineni2019-04-081-5/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates tegra_spi_soc_data structure to maintain and implement SPI HW feature differences between different Tegra chips and also creates a separate compatible string for T124/T210. Tegra210 and later has a separate interrupt mask register SPI_INTR_MASK for enabling or disabling interrupts while Tegra124 and prior uses interrupt enable bits in SPI_DMA_CTL register. This patch creates flag has_intr_mask_reg in tegra_spi_soc_data to identify this and implements accordingly. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: tegra114: add 3 wire transfer mode supportSowjanya Komatineni2019-04-081-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds 3 wire transfer support to SPI mode list along with its implementation. 3 wire or Bi-directional mode uses only one serial data pin for the transfer. SPI in master mode uses MOSI data line only and MISO data line is not used. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: tegra114: add dual mode supportSowjanya Komatineni2019-04-081-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dual mode SPI transfer. Dual mode uses both MOSI and MISO lines in parallel where the data is interleaved on MOSI and MISO lines increasing the throughput. Packet from Tx FIFO is transmitted on both MOSI and MISO lines and packet to Rx FIFO is received from both MOSI and MISO lines. Even bits are transmitted or received on the MOSI data line and odd bits are transmitted or received on the MISO data line. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: tegra114: set bus number based on idSowjanya Komatineni2019-04-051-0/+4
| | | | | | | | | | | | | | This patch sets SPI device id from the device tree as the bus number. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: tegra114: use unpacked mode for below 4 bytesSowjanya Komatineni2019-04-051-1/+2
| | | | | | | | | | | | | | | | | | | | Packed mode expects minimum transfer length of 4 bytes. This patch fixes this by using unpacked mode for transfers less than 4 bytes. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: tegra114: set supported bits per wordSowjanya Komatineni2019-04-051-0/+1
| | | | | | | | | | | | | | | | | | | | Tegra SPI supports 4 through 32 bits per word. This patch sets bits_per_word_mask accordingly to support transfer with these bits per word. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: tegra114: dump SPI registers during timeoutSowjanya Komatineni2019-04-051-0/+18
| | | | | | | | | | | | | | | | This patch dumps SPI registers on transfer error or timeout for debug purpose. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * Merge branch 'spi-5.1' into spi-5.2Mark Brown2019-04-051-62/+146
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| * | spi: tegra114: add SPI_LSB_FIRST supportSowjanya Komatineni2019-04-011-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra SPI controller supports lsb first mode. Default is MSB bit first and on selection of SPI_LSB_FIRST through SPI mode transmission happens with LSB bit first. This patch adds SPI_LSB_FIRST flag to mode_bits and also configures it on request. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: tegra114: use packed mode for 32 bits per wordSowjanya Komatineni2019-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fixes: Use packed mode for 32 bits per word transfers to increase performance as each packet is a full 32-bit word. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | spi: tegra114: fix PIO transferSowjanya Komatineni2019-05-021-2/+3
| |/ |/| | | | | | | | | | | | | This patch fixes PIO mode transfer to use PIO bit in SPI_COMMAND1 register. Current driver uses DMA_EN instead of PIO bit. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: avoid reset call in atomic contextSowjanya Komatineni2019-04-051-4/+5
| | | | | | | | | | | | | | This patch moves SPI controller reset out of spin lock. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: de-assert CS before SPI mode changeSowjanya Komatineni2019-04-051-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With SW CS, during the transfer completion CS is de-asserted by writing default command1 register value to SPI_COMMAND1 register. With this both mode and CS state are set at the same time and if current transfer mode is different to default SPI mode and if mode change happens prior to CS de-assert, clock polarity can change while CS is active before transfer finishes. This causes Slave to see spurious clock edges resulting in data mismatch. This patch fixes this by de-asserting CS before writing SPI_COMMAND1 to its default value so through out the transfer it will be in same SPI mode. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: reset controller on probeSowjanya Komatineni2019-04-011-14/+18
| | | | | | | | | | | | | | | | Fixes: SPI driver can be built as module so perform SPI controller reset on probe to make sure it is in valid state before initiating transfer. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: configure dma burst size to fifo trig levelSowjanya Komatineni2019-04-011-22/+30
| | | | | | | | | | | | | | | | | | | | | | | | Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels to avoid mismatch. SPI FIFO trigger levels are calculated based on the transfer length. So this patch moves DMA slave configuration to happen before start of DMAs. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: flush fifosSowjanya Komatineni2019-04-011-9/+30
| | | | | | | | | | | | | | | | Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO overflow or underrun errors. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: terminate dma and reset on transfer timeoutSowjanya Komatineni2019-04-011-0/+9
| | | | | | | | | | | | | | | | Fixes: terminate DMA and perform controller reset on transfer timeout to clear the FIFO's and errors. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: fix for unpacked mode transfersSowjanya Komatineni2019-04-011-7/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes: computation of actual bytes to fill/receive in/from FIFO in unpacked mode when transfer length is not a multiple of requested bits per word. unpacked mode transfers fails when the transfer includes partial bytes in the last word. Total words to be written/read to/from FIFO is computed based on transfer length and bits per word. Unpacked mode includes 0 padding bytes for partial words to align with bits per word and these extra bytes are also accounted for calculating bytes left to transfer in the current driver. This causes extra bytes access of tx/rx buffers along with buffer index position crossing actual length where remain_len becomes negative and due to unsigned type, negative value is a 32 bit representation of signed value and transferred bytes never meets the actual transfer length resulting in transfer timeout and a hang. This patch fixes this with proper computation of the actual bytes to fill in FIFO during transmit and the actual bytes to read from FIFO during receive ignoring 0 padded bytes. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: tegra114: clear packed bit for unpacked modeSowjanya Komatineni2019-04-011-0/+2
|/ | | | | | | | | | | Fixes: Clear packed bit when not using packed mode. Packed bit is not cleared when not using packed mode. This results in transfer timeouts for the unpacked mode transfers followed by the packed mode transfers. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: tegra114: correct register name in definitionRalf Ramsauer2017-10-091-3/+3
| | | | | | | | According to "Tegra K1 Processor Technical Reference Manual" (p. 2448), bit 20 of SPI_COMMAND1 is called CS_SW_VAL and not CS_SS_VAL. Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: tegra114: explicitly request exclusive reset controlPhilipp Zabel2017-07-191-1/+1
| | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Mark Brown <broonie@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-spi@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: tegra: fix spelling mistake: "trasfer" -> "transfer"Colin Ian King2017-04-241-1/+1
| | | | | | | trivial fix to spelling mistake in dbg_err messages Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: drop owner assignment from platform_driversWolfram Sang2014-10-201-1/+0Star
| | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* spi: tegra114: Fix checkpatch issueJingoo Han2014-09-031-0/+9
| | | | | | | | | Fix the following checkpatch warnings. WARNING: Missing a blank line after declarations Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: tegra114: Make of_device_id array constJingoo Han2014-05-071-1/+1
| | | | | | | | | Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
*-. Merge remote-tracking branches 'spi/topic/sunxi', 'spi/topic/tegra114', ↵Mark Brown2014-03-301-2/+2
|\ \ | | | | | | | | | 'spi/topic/ti-qspi', 'spi/topic/ti-ssp', 'spi/topic/topcliff-pch', 'spi/topic/txx9', 'spi/topic/xcomm' and 'spi/topic/xfer' into spi-next
| | * spi: tegra114: Use list_is_last() instead of open-codedAxel Lin2014-02-031-2/+2
| |/ | | | | | | | | | | | | For better readability, and then we can remove the comment for last transfer. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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*---. \ Merge remote-tracking branches 'spi/topic/imx', 'spi/topic/init', ↵Mark Brown2014-03-301-1/+0Star
|\ \ \ \ | | |_|/ | |/| | | | | | 'spi/topic/mpc512x-psc', 'spi/topic/mpc52xx', 'spi/topic/mxs', 'spi/topic/nuc900', 'spi/topic/oc-tiny' and 'spi/topic/octeon' into spi-next
| | * | spi: delete non-required instances of include <linux/init.h>Paul Gortmaker2014-02-031-1/+0Star
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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*-. \ \ Merge remote-tracking branches 'spi/topic/bus-num', 'spi/topic/cleanup', ↵Mark Brown2014-03-301-19/+3Star
|\ \ \ \ | |_|/ / |/| | / | | |/ 'spi/topic/clps711x', 'spi/topic/coldfire', 'spi/topic/completion' and 'spi/topic/davinci' into spi-next
| | * spi: Remove duplicate code to check chip_selectAxel Lin2014-02-121-2/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | In spi_add_device(), we have the code to validate spi->chip_select. So remove the duplicate code in various drivers. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
| | * spi: tegra114: Convert to use master->max_speed_hzAxel Lin2014-02-111-16/+3Star
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | Use master->max_speed_hz instead of tspi->spi_max_frequency, so spi core will handle checking transfer speed. In additional, since commit 052eb2d49006 'spi: core: Set max_speed_hz of spi_device default to max_speed_hz of controller', spi core will also set default spi->max_speed_hz if it is not set. So remove the duplicate code in tegra_spi_setup. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
| * spi: Remove explictly set bus_num and num_chipselect to default settingAxel Lin2014-02-161-1/+0Star
|/ | | | | | | | | | | | | The purpose of commit 1e8a52e18cfb "spi: By default setup spi_masters with 1 chipselect and dynamics bus number" is to avoid setting default value for bus_num and num_chipselect in spi master drivers. So let's remove the duplicate code. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-By: David Daney <david.daney@cavium.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* Merge tag 'spi-v3.14-2' of ↵Linus Torvalds2014-01-251-64/+34Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "A respun version of the merges for the pull request previously sent with a few additional fixes. The last two merges were fixed up by hand since the branches have moved on and currently have the prior merge in them. Quite a busy release for the SPI subsystem, mostly in cleanups big and small scattered through the stack rather than anything else: - New driver for the Broadcom BC63xx HSSPI controller - Fix duplicate device registration for ACPI - Conversion of s3c64xx to DMAEngine (this pulls in platform and DMA changes upon which the transiton depends) - Some small optimisations to reduce the amount of time we hold locks in the datapath, eliminate some redundant checks and the size of a spi_transfer - Lots of fixes, cleanups and general enhancements to drivers, especially the rspi and Atmel drivers" * tag 'spi-v3.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (112 commits) spi: core: Fix transfer failure when master->transfer_one returns positive value spi: Correct set_cs() documentation spi: Clarify transfer_one() w.r.t. spi_finalize_current_transfer() spi: Spelling s/finised/finished/ spi: sc18is602: Convert to use bits_per_word_mask spi: Remove duplicate code to set default bits_per_word setting spi/pxa2xx: fix compilation warning when !CONFIG_PM_SLEEP spi: clps711x: Add MODULE_ALIAS to support module auto-loading spi: rspi: Add missing clk_disable() calls in error and cleanup paths spi: rspi: Spelling s/transmition/transmission/ spi: rspi: Add support for specifying CPHA/CPOL spi/pxa2xx: initialize DMA channels to -1 to prevent inadvertent match spi: rspi: Add more QSPI register documentation spi: rspi: Add more RSPI register documentation spi: rspi: Remove dependency on DMAE for SHMOBILE spi/s3c64xx: Correct indentation spi: sh: Use spi_sh_clear_bit() instead of open-coded spi: bitbang: Grammar s/make to make/to make/ spi: sh-hspi: Spelling s/recive/receive/ spi: core: Improve tx/rx_nbits check comments ...
| * spi: tegra114: use u32 for 32-bit register valuesMichal Nazarewicz2013-12-091-64/+34Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously used “unsigned long” may lead to confusion should the code be compiled for 64-bit machine. This commit also removes some unused fields of the tegra_spi_data structure as well as removes duplicated #defines. Signed-off-by: Michal Nazarewicz <mina86@mina86.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | spi: tegra: convert to standard DMA DT bindingsStephen Warren2013-12-121-31/+17Star
| | | | | | | | | | | | | | | | | | | | By using dma_request_slave_channel_or_err(), the DMA slave ID can be looked up from standard DT properties, and squirrelled away during channel allocation. Hence, there's no need to use a custom DT property to store the slave ID. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
* | spi: tegra: use reset frameworkStephen Warren2013-12-121-5/+13
|/ | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
* tree-wide: use reinit_completion instead of INIT_COMPLETIONWolfram Sang2013-11-151-3/+3
| | | | | | | | | | | | Use this new function to make code more comprehensible, since we are reinitialzing the completion, not initializing. [akpm@linux-foundation.org: linux-next resyncs] Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Cc: Ingo Molnar <mingo@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge remote-tracking branch 'spi/topic/tegra114' into spi-nextMark Brown2013-10-251-17/+68
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| * spi/tegra114: Correct support for cs_changeRhyland Klein2013-09-271-17/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tegra114 driver wasn't currently handling the cs_change functionality. cs_change is meant to invert the decisions of whether or not to deactivate CS after each transfer. Without cs_change, after every transfer (other than the last in the message) the normal behavior is to leave CS active. For the last transfer, normally CS is deactivated when the transfer is complete. With cs_change set on a transfer (other than last one) CS would be deactivated and the next transfer would need to activate it again. If cs_change was set on the last tranfer in a message, then CS would be left active when the message compeleted. Also, this builds in logic so that if a different device tries to start a transfer while CS is active from a different device, it will abort the previous transfer and start a new one for the new device. This splits tegra_spi_start_transfer_one into 2 functions, the new one being tegra_spi_setup_transfer_one. The setup function is safe to call on all transfers, sets up for the transfer, and handles the special case of the first transfer in a message. In this special case, it needs to know whether or not it needs to activate CS. This work was based on the spi-atmel driver. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | Merge remote-tracking branch 'spi/topic/tegra' into spi-nextMark Brown2013-10-251-1/+1
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| * | spi: tegra: Use DIV_ROUND_UP instead of open codedAxel Lin2013-09-171-1/+1
| |/ | | | | | | | | | | | | This also makes the intention more clear. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-06-10 08:00:10 +0200