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| author | Pavel Dovgalyuk | 2022-11-01 06:29:44 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2022-11-08 01:04:25 +0100 |
| commit | 4525ea7e0caa4aa6317204cd977179dea972cf6d (patch) | |
| tree | 7f8973dd706a751a9b138a7fc8cb77317da09648 /target/mips/tcg/mxu_translate.c | |
| parent | target/mips: Cast offset field of Octeon BBIT to int16_t (diff) | |
| download | qemu-4525ea7e0caa4aa6317204cd977179dea972cf6d.tar.gz qemu-4525ea7e0caa4aa6317204cd977179dea972cf6d.tar.xz qemu-4525ea7e0caa4aa6317204cd977179dea972cf6d.zip | |
target/mips: Enable LBX/LWX/* instructions for Octeon
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target/mips/tcg/mxu_translate.c')
0 files changed, 0 insertions, 0 deletions