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| author | Jonathan Behrens | 2019-05-08 19:38:35 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:25 +0200 |
| commit | 1e0d985fa9136a563168a3da66f3d17820404ee2 (patch) | |
| tree | edfeec3a5ef58a435424087a9cfa8f5020429127 /target/riscv/Makefile.objs | |
| parent | target/riscv: More accurate handling of `sip` CSR (diff) | |
| download | qemu-1e0d985fa9136a563168a3da66f3d17820404ee2.tar.gz qemu-1e0d985fa9136a563168a3da66f3d17820404ee2.tar.xz qemu-1e0d985fa9136a563168a3da66f3d17820404ee2.zip | |
target/riscv: Only flush TLB if SATP.ASID changes
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/Makefile.objs')
0 files changed, 0 insertions, 0 deletions