diff options
| author | Alistair Francis | 2020-12-16 19:22:29 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:44 +0100 |
| commit | c0a635f3973d974befb954463287786fd988bb64 (patch) | |
| tree | b06eb031a496452bcd61e464ccb707dad2d82289 /target/riscv | |
| parent | hw/riscv: Expand the is 32-bit check to support more CPUs (diff) | |
| download | qemu-c0a635f3973d974befb954463287786fd988bb64.tar.gz qemu-c0a635f3973d974befb954463287786fd988bb64.tar.xz qemu-c0a635f3973d974befb954463287786fd988bb64.zip | |
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..9c064f3094 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -44,6 +44,12 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) |