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path: root/hw/riscv/sifive_u.c
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* hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza2022-10-171-0/+3
* hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow2022-05-241-20/+4Star
* hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI2022-05-241-2/+2
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-291-1/+1
* hw/riscv: Use error_fatal for SoC realisationAlistair Francis2022-01-081-1/+1
* hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2021-12-151-1/+1
* hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster2021-12-151-1/+12
* hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1Star
* hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2Star
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-201-3/+6
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-201-1/+1
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-201-1/+54
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-1/+1
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0Star
* hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng2021-07-151-2/+3
* hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng2021-07-151-2/+5
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-4/+2Star
* hw/riscv: Support the official PLIC DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-3/+3
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-7/+4Star
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-041-2/+41
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-041-0/+52
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-5/+5
* hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng2021-01-161-5/+1Star
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-181-5/+5
* hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis2020-12-181-25/+30
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-181-1/+1
* hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel2020-12-181-0/+15
* vl: make qemu_get_machine_opts staticPaolo Bonzini2020-12-151-4/+2Star
* hw/riscv: sifive_u: Allow passing custom DTBAnup Patel2020-11-031-8/+20
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-2/+8
* hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis2020-10-221-5/+13
* sifive_u: Register "start-in-flash" as class propertyEduardo Habkost2020-09-221-8/+8
* sifive_u: Rename memmap enum constantsEduardo Habkost2020-09-181-78/+78
* hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-101-0/+30
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+2
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-101-0/+2
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-251-1/+1
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1
* hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2020-08-221-2/+2
* hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng2020-08-221-0/+22
* hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster2020-07-211-0/+1
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-141-1/+1
* RISC-V: Support 64 bit start addressAtish Patra2020-07-141-1/+5
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-141-5/+15
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