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path: root/hw/riscv/virt.c
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* hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell2021-09-011-13/+20
* hw/riscv: virt: Move flash node to rootBin Meng2021-09-011-1/+1
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0Star
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-4/+2Star
* hw/riscv: Support the official PLIC DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-2/+5
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* hw/riscv: allow ramfb on virtAsherah Connor2021-03-231-0/+3
* hw/riscv: Add fw_cfg support to virtAsherah Connor2021-03-231-0/+30
* hw/riscv: migrate fdt field to generic MachineStateAlex Bennée2021-03-101-10/+10
* hw/riscv: virt: Map high mmio for PCIeBin Meng2021-03-041-2/+33
* hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng2021-03-041-0/+10
* hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng2021-03-041-7/+7
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3Star
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-4/+4
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-181-4/+5
* hw/riscv: virt: Remove compile time XLEN checksAlistair Francis2020-12-181-15/+17
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-181-1/+1
* riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-181-1/+1
* vl: make qemu_get_machine_opts staticPaolo Bonzini2020-12-151-4/+2Star
* hw/riscv: virt: Allow passing custom DTBAnup Patel2020-11-031-7/+20
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-3/+8
* hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+2
* hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel2020-08-251-227/+299
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-251-1/+1
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1
* hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2020-08-221-2/+2
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-141-1/+1
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-141-3/+9
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-141-1/+6
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-141-37/+3Star
* hw/riscv: virt: Sort the SoC memmap table entriesBin Meng2020-07-141-3/+3
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-2/+2
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster2020-06-151-4/+3Star
* sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster2020-06-151-2/+2
* qdev: Convert uses of qdev_create() manuallyMarkus Armbruster2020-06-151-2/+2
* qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster2020-06-151-2/+2
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-151-2/+2
* hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng2020-06-031-10/+10
* hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé2020-05-181-1/+1
* qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2020-05-151-3/+2Star
* hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel2020-04-291-1/+1
* hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng2020-04-291-0/+4
* hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-271-1/+1
* riscv: virt: Allow PCI address 0Bin Meng2020-02-271-0/+1
* riscv: virt: Use Goldfish RTC deviceAnup Patel2020-02-101-0/+16
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