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path: root/hw/riscv/virt.c
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* hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+2
* hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel2020-08-251-227/+299
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-251-1/+1
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1
* hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2020-08-221-2/+2
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-141-1/+1
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-141-3/+9
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-141-1/+6
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-141-37/+3Star
* hw/riscv: virt: Sort the SoC memmap table entriesBin Meng2020-07-141-3/+3
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-2/+2
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster2020-06-151-4/+3Star
* sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster2020-06-151-2/+2
* qdev: Convert uses of qdev_create() manuallyMarkus Armbruster2020-06-151-2/+2
* qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster2020-06-151-2/+2
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-151-2/+2
* hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng2020-06-031-10/+10
* hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé2020-05-181-1/+1
* qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2020-05-151-3/+2Star
* hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel2020-04-291-1/+1
* hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng2020-04-291-0/+4
* hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-271-1/+1
* riscv: virt: Allow PCI address 0Bin Meng2020-02-271-0/+1
* riscv: virt: Use Goldfish RTC deviceAnup Patel2020-02-101-0/+16
* riscv/virt: Add syscon reboot and poweroff DT nodesAnup Patel2020-02-101-4/+22
* hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-251-1/+2
* RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt2019-11-251-1/+4
* riscv/virt: Increase flash sizeAlistair Francis2019-11-141-1/+1
* riscv/virt: Jump to pflash if specifiedAlistair Francis2019-10-281-1/+10
* riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2019-10-281-0/+86
* riscv/virt: Manually define the machineAlistair Francis2019-10-281-6/+24
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-281-2/+0Star
* riscv: hw: Change create_fdt() to return voidBin Meng2019-09-171-7/+4Star
* riscv: hw: Remove not needed PLIC properties in device treeBin Meng2019-09-171-2/+0Star
* riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng2019-09-171-12/+12
* riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng2019-09-171-3/+0Star
* Include sysemu/sysemu.h a lot lessMarkus Armbruster2019-08-161-0/+1
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-1/+0Star
* hw/riscv: Load OpenSBI as the default firmwareAlistair Francis2019-07-181-3/+8
* hw/riscv: Replace global smp variables with machine smp propertiesLike Xu2019-07-051-0/+1
* hw/riscv: Add support for loading a firmwareAlistair Francis2019-06-271-0/+4
* hw/riscv: Split out the boot functionsAlistair Francis2019-06-271-46/+5Star
* riscv: virt: Add cpu-topology DT node.Atish Patra2019-06-261-2/+20
* riscv: virt: Correct pci "bus-range" encodingBin Meng2019-06-241-1/+1
* riscv: virt: Allow specifying a CPU via commandlineAlistair Francis2019-05-241-1/+2
* target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens2019-05-241-1/+0Star
* riscv: Ensure the kernel start address is correctly castAlistair Francis2019-02-121-1/+1
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