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* riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-181-24/+57
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-184-34/+24Star
* hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis2020-12-181-25/+30
* hw/riscv: spike: Remove compile time XLEN checksAlistair Francis2020-12-181-21/+24
* hw/riscv: virt: Remove compile time XLEN checksAlistair Francis2020-12-181-15/+17
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-184-28/+34
* riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-181-1/+1
* riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-181-1/+1
* hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis2020-12-181-1/+11
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-181-0/+21
* hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel2020-12-181-0/+15
* vl: make qemu_get_machine_opts staticPaolo Bonzini2020-12-152-8/+4Star
* vl: extract softmmu/datadir.cPaolo Bonzini2020-12-101-0/+1
* riscv: do not use ram_size globalPaolo Bonzini2020-12-101-2/+3
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+6
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-6/+44
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-1/+10
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-032-3/+7
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-032-5/+9
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-032-0/+19
* hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng2020-11-031-0/+18
* hw/riscv: virt: Allow passing custom DTBAnup Patel2020-11-031-7/+20
* hw/riscv: sifive_u: Allow passing custom DTBAnup Patel2020-11-031-8/+20
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-226-15/+42
* hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis2020-10-221-0/+9
* hw/riscv: Return the end address of the loaded firmwareAlistair Francis2020-10-221-11/+17
* hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis2020-10-221-5/+13
* load_elf: Remove unused address variables from callersBALATON Zoltan2020-09-261-4/+4
* sifive_u: Register "start-in-flash" as class propertyEduardo Habkost2020-09-221-8/+8
* sifive_e: Register "revb" as class propertyEduardo Habkost2020-09-221-5/+6
* sifive_u: Rename memmap enum constantsEduardo Habkost2020-09-181-78/+78
* sifive_e: Rename memmap enum constantsEduardo Habkost2020-09-181-41/+41
* hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng2020-09-101-29/+29
* hw/riscv: Drop CONFIG_SIFIVEBin Meng2020-09-101-9/+5Star
* hw/riscv: Always build riscv_hart.cBin Meng2020-09-102-10/+1Star
* hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-104-102/+2Star
* hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-105-197/+4Star
* hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-104-266/+1Star
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-107-529/+9Star
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-108-272/+10Star
* hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-105-406/+2Star
* hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-103-192/+1Star
* hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-103-170/+1Star
* hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-104-127/+2Star
* hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-102-0/+31
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-106-16/+28
* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+14
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+39
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-102-0/+16
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-102-0/+24
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