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* hw: aspeed: Introduce common UART init functionPeter Delevoryas2022-05-251-0/+1
* hw: aspeed: Add uarts_num SoC attributePeter Delevoryas2022-05-251-0/+1
* hw: aspeed: Add missing UART'sPeter Delevoryas2022-05-251-0/+8
* aspeed: Introduce a get_irq AspeedSoCClass methodCédric Le Goater2022-05-251-0/+3
* aspeed/soc : Add AST1030 supportSteven Lee2022-05-021-0/+3
* aspeed: Add eMMC Boot Controller stubJoel Stanley2022-05-021-0/+1
* hw/core: Move the ARM sysbus-fdt to coreAlistair Francis2022-04-291-37/+0Star
* hw/arm/smmuv3: Cache event fault recordJean-Philippe Brucker2022-04-281-0/+1
* hw/arm/virt: Support TCG GICv4Peter Maydell2022-04-221-2/+10
* hw/arm/virt: Abstract out calculation of redistributor region capacityPeter Maydell2022-04-221-2/+7
* hw/arm/exynos4210: Drop Exynos4210Irq structPeter Maydell2022-04-211-6/+0Star
* hw/arm/exynos4210: Put combiners into state structPeter Maydell2022-04-211-0/+3
* hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()Peter Maydell2022-04-211-2/+4
* hw/arm/exynos4210: Don't connect multiple lines to external GIC inputsPeter Maydell2022-04-211-1/+1
* hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()Peter Maydell2022-04-211-0/+9
* hw/arm/exynos4210: Delete unused macro definitionsPeter Maydell2022-04-211-4/+0Star
* hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.cPeter Maydell2022-04-211-11/+0Star
* hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq structPeter Maydell2022-04-211-1/+0Star
* hw/arm/exynos4210: Put external GIC into state structPeter Maydell2022-04-211-0/+2
* hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.cPeter Maydell2022-04-211-4/+0Star
* hw/arm/exynos4210: Coalesce board_irqs and irq_tablePeter Maydell2022-04-211-6/+2Star
* hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq structPeter Maydell2022-04-211-1/+0Star
* hw/arm/exynos4210: Put a9mpcore device into state structPeter Maydell2022-04-211-0/+2
* hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate devicePeter Maydell2022-04-211-0/+1
* hw/arm: versal: Connect the CRLEdgar E. Iglesias2022-04-211-0/+4
* hw/arm: versal: Add the Cortex-R5FsEdgar E. Iglesias2022-04-211-0/+10
* hw/arm: versal: Create an APU CPU ClusterEdgar E. Iglesias2022-04-211-0/+2
* hw/arm/xlnx-zynqmp: Connect 4 TTC timersEdgar E. Iglesias2022-04-211-0/+4
* hw/arm/xlnx-zynqmp: Connect the ZynqMP APU ControlEdgar E. Iglesias2022-03-181-1/+3
* hw/arm/xlnx-zynqmp: Connect the ZynqMP CRFEdgar E. Iglesias2022-03-181-0/+2
* hw/arm/xlnx-zynqmp: Add an unimplemented SERDES areaEdgar E. Iglesias2022-03-181-1/+1
* hw/arm/virt: Disable LPA2 for -machine virt-6.2Richard Henderson2022-03-071-0/+1
* ast2600: Add Secure Boot Controller modelJoel Stanley2022-02-261-0/+3
* hw/arm/boot: Drop nb_cpus field from arm_boot_infoPeter Maydell2022-02-081-1/+0Star
* hw/arm/boot: Don't write secondary boot stub if using PSCIPeter Maydell2022-02-081-0/+3
* hw/arm/versal: Let boot.c handle PSCI enablementPeter Maydell2022-02-081-1/+0Star
* hw/arm/boot: Support setting psci-conduit based on guest ELPeter Maydell2022-02-081-0/+10
* hw/arm/xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQsFrancisco Iglesias2022-02-081-0/+2
* hw/arm/xlnx-versal: Connect the OSPI flash memory controller modelFrancisco Iglesias2022-01-281-0/+20
* hw/arm/xlnx-versal: Connect Versal's PMC SLCRFrancisco Iglesias2022-01-281-0/+5
* hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC modelsFrancisco Iglesias2022-01-281-2/+3
* hw/arm/aspeed: Add the i3c device to the AST2600 SoCTroy Lee2022-01-201-0/+3
* hw/arm/virt: Add a control for the the highmem redistributorsMarc Zyngier2022-01-201-1/+3
* hw/arm/virt: Add a control for the the highmem PCIe MMIOMarc Zyngier2022-01-201-0/+1
* hw/arm: add control knob to disable kaslr_seed via DTBAlex Bennée2022-01-181-0/+1
* Add dummy Aspeed AST2600 Display Port MCU (DPMCU)Troy Lee2022-01-071-0/+2
* hw/arm: Add Nuvoton SD module to boardShengtan Mao2021-11-021-0/+2
* hw/arm/virt: Only describe cpu topology since virt-6.2Yanan Wang2021-10-211-1/+3
* hw/arm: Integrate ADC model into Aspeed SoCAndrew Jeffery2021-10-121-0/+2
* hw/arm: xlnx-zcu102: Add Xilinx eFUSE deviceTong Ho2021-09-301-0/+3
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