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path: root/include/hw/riscv/opentitan.h
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* hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis2022-09-261-0/+2
* hw/riscv: opentitan: bump opentitan versionWilfred Mallawa2022-09-071-5/+6
* riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa2022-04-221-9/+21
* hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa2022-03-031-1/+3
* hw/riscv: opentitan: Update to the latest buildAlistair Francis2021-10-221-3/+3
* hw/riscv: opentitan: Add the flash aliasAlistair Francis2021-07-151-0/+2
* hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis2021-07-151-0/+1
* hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis2021-06-241-1/+4
* hw/opentitan: Update the interrupt layoutAlistair Francis2021-05-111-8/+8
* riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-181-6/+17
* Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost2020-09-181-3/+1Star
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-2/+2
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-2/+4
* opentitan: Rename memmap enum constantsEduardo Habkost2020-08-271-19/+19
* riscv/opentitan: Connect the UART deviceAlistair Francis2020-06-191-0/+13
* riscv/opentitan: Connect the PLIC deviceAlistair Francis2020-06-191-0/+3
* riscv: Initial commit of OpenTitan machineAlistair Francis2020-06-031-0/+68