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* Merge remote-tracking branch ↵Peter Maydell2021-03-146-2/+196
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20210314' into staging target-arm queue: * versal: Support XRAMs and XRAM controller * smmu: Various minor bug fixes * SVE emulation: fix bugs handling odd vector lengths * allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value * tests/acceptance: fix orangepi-pc acceptance tests * hw/timer/sse-timer: Propagate eventual error in sse_timer_realize() * hw/arm/virt: KVM: The IPA lower bound is 32 * npcm7xx: support MFT module * pl110, pxa2xx_lcd: tidy up template headers # gpg: Signature made Sun 14 Mar 2021 13:17:43 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210314: (39 commits) hw/display/pxa2xx: Inline template header hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header hw/display/pxa2xx: Apply brace-related coding style fixes to template header hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h hw/display/pxa2xx_lcd: Remove dest_width state field hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces hw/display/pl110: Remove use of BITS from pl110_template.h hw/display/pl110: Pull included-once parts of template header into pl110.c hw/display/pl110: Remove dead code for non-32-bpp surfaces tests/qtest: Test PWM fan RPM using MFT in PWM test hw/arm: Connect PWM fans in NPCM7XX boards hw/arm: Add MFT device to NPCM7xx Soc hw/misc: Add NPCM7XX MFT Module hw/misc: Add GPIOs for duty in NPCM7xx PWM hw/arm/virt: KVM: The IPA lower bound is 32 accel: kvm: Fix kvm_type invocation hw/timer/sse-timer: Propagate eventual error in sse_timer_realize() tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests tests/acceptance: update sunxi kernel from armbian to 5.10.16 tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: Connect PWM fans in NPCM7XX boardsHao Wu2021-03-121-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds fan_splitters (split IRQs) in NPCM7XX boards. Each fan splitter corresponds to 1 PWM output and can connect to multiple fan inputs (MFT devices). In NPCM7XX boards(NPCM750 EVB and Quanta GSJ boards), we initializes these splitters and connect them to their corresponding modules according their specific device trees. Reviewed-by: Doug Evans <dje@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210311180855.149764-5-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: Add MFT device to NPCM7xx SocHao Wu2021-03-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the recently implemented MFT device to the NPCM7XX SoC file. Reviewed-by: Doug Evans <dje@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210311180855.149764-4-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc: Add NPCM7XX MFT ModuleHao Wu2021-03-121-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements Multi Function Timer (MFT) module for NPCM7XX. This module is mainly used to configure PWM fans. It has just enough functionality to make the PWM fan kernel module work. The module takes two input, the max_rpm of a fan (modifiable via QMP) and duty cycle (a GPIO from the PWM module.) The actual measured RPM is equal to max_rpm * duty_cycle / NPCM7XX_PWM_MAX_DUTY. The RPM is measured as a counter compared to a prescaled input clock. The kernel driver reads this counter and report to user space. Refs: https://github.com/torvalds/linux/blob/master/drivers/hwmon/npcm750-pwm-fan.c Reviewed-by: Doug Evans <dje@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210311180855.149764-3-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc: Add GPIOs for duty in NPCM7xx PWMHao Wu2021-03-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds GPIOs in NPCM7xx PWM module for its duty values. The purpose of this is to connect it to the MFT module to provide an input for measuring a PWM fan's RPM. Each PWM module has NPCM7XX_PWM_PER_MODULE of GPIOs, each one corresponds to one PWM instance and can connect to multiple fan instances in MFT. Reviewed-by: Doug Evans <dje@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210311180855.149764-2-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * accel: kvm: Fix kvm_type invocationAndrew Jones2021-03-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to commit f2ce39b4f067 a MachineClass kvm_type method only needed to be registered to ensure it would be executed. With commit f2ce39b4f067 a kvm-type machine property must also be specified. hw/arm/virt relies on the kvm_type method to pass its selected IPA limit to KVM, but this is not exposed as a machine property. Restore the previous functionality of invoking kvm_type when it's present. Fixes: f2ce39b4f067 ("vl: make qemu_get_machine_opts static") Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20210310135218.255205-2-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: versal: Add support for the XRAMsEdgar E. Iglesias2021-03-121-0/+13
| | | | | | | | | | | | | | | | | | | | Connect the support for the Versal Accelerator RAMs (XRAMs). Reviewed-by: Luc Michel <luc@lmichel.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210308224637.2949533-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc: versal: Add a model of the XRAM controllerEdgar E. Iglesias2021-03-121-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a model of the Xilinx Versal Accelerator RAM (XRAM). This is mainly a stub to make firmware happy. The size of the RAMs can be probed. The interrupt mask logic is modelled but none of the interrups will ever be raised unless injected. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210310' ↵Peter Maydell2021-03-122-1/+7
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ppc patch queue for 2021-03-10 Next batch of patches for the ppc target and machine types. Includes: * Several cleanups for sm501 from Peter Maydell * An update to the SLOF guest firmware * Improved handling of hotplug failures in spapr, associated cleanups to the hotplug handling code * Several etsec fixes and cleanups from Bin Meng * Assorted other fixes and cleanups # gpg: Signature made Wed 10 Mar 2021 04:08:53 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.0-20210310: spapr.c: send QAPI event when memory hotunplug fails spapr.c: remove duplicated assert in spapr_memory_unplug_request() target/ppc: fix icount support on Book-e vms accessing SPRs qemu_timer.c: add timer_deadline_ms() helper spapr_pci.c: add 'unplug already in progress' message for PCI unplug spapr.c: add 'unplug already in progress' message for PHB unplug hw/ppc: e500: Add missing <ranges> in the eTSEC node hw/net: fsl_etsec: Fix build error when HEX_DUMP is on spapr_drc.c: use DRC reconfiguration to cleanup DIMM unplug state spapr_drc.c: add hotunplug timeout for CPUs spapr_drc.c: introduce unplug_timeout_timer target/ppc: Fix bcdsub. emulation when result overflows docs/system: Extend PPC section spapr: rename spapr_drc_detach() to spapr_drc_unplug_request() spapr_drc.c: use spapr_drc_release() in isolate_physical/set_unusable pseries: Update SLOF firmware image spapr_drc.c: do not call spapr_drc_detach() in drc_isolate_logical() hw/display/sm501: Inline template header into C file hw/display/sm501: Expand out macros in template header hw/display/sm501: Remove dead code for non-32-bit RGB surfaces Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * spapr.c: send QAPI event when memory hotunplug failsDaniel Henrique Barboza2021-03-091-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent changes allowed the pSeries machine to rollback the hotunplug process for the DIMM when the guest kernel signals, via a reconfiguration of the DR connector, that it's not going to release the LMBs. Let's also warn QAPI listerners about it. One place to do it would be right after the unplug state is cleaned up, spapr_clear_pending_dimm_unplug_state(). This would mean that the function is now doing more than cleaning up the pending dimm state though. This patch does the following changes in spapr.c: - send a QAPI event to inform that we experienced a failure in the hotunplug of the DIMM; - rename spapr_clear_pending_dimm_unplug_state() to spapr_memory_unplug_rollback(). This is a better fit for what the function is now doing, and it makes callers care more about what the function goal is and less about spapr.c internals such as clearing the pending dimm unplug state. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210302141019.153729-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * spapr_drc.c: use DRC reconfiguration to cleanup DIMM unplug stateDaniel Henrique Barboza2021-03-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handling errors in memory hotunplug in the pSeries machine is more complex than any other device type, because there are all the complications that other devices has, and more. For instance, determining a timeout for a DIMM hotunplug must consider if it's a Hash-MMU or a Radix-MMU guest, because Hash guests takes longer to hotunplug DIMMs. The size of the DIMM is also a factor, given that longer DIMMs naturally takes longer to be hotunplugged from the kernel. And there's also the guest memory usage to be considered: if there's a process that is consuming memory that would be lost by the DIMM unplug, the kernel will postpone the unplug process until the process finishes, and then initiate the regular hotunplug process. The first two considerations are manageable, but the last one is a deal breaker. There is no sane way for the pSeries machine to determine the memory load in the guest when attempting a DIMM hotunplug - and even if there was a way, the guest can start using all the RAM in the middle of the unplug process and invalidate our previous assumptions - and in result we can't even begin to calculate a timeout for the operation. This means that we can't implement a viable timeout mechanism for memory unplug in pSeries. Going back to why we would consider an unplug timeout, the reason is that we can't know if the kernel is giving up the unplug. Turns out that, sometimes, we can. Consider a failed memory hotunplug attempt where the kernel will error out with the following message: 'pseries-hotplug-mem: Memory indexed-count-remove failed, adding any removed LMBs' This happens when there is a LMB that the kernel gave up in removing, and the LMBs previously marked for removal are now being added back. This happens in the pseries kernel in [1], dlpar_memory_remove_by_ic() into dlpar_add_lmb(), and after that update_lmb_associativity_index(). In this function, the kernel is configuring the LMB DRC connector again. Note that this is a valid usage in LOPAR, as stated in section "ibm,configure-connector RTAS Call": 'A subsequent sequence of calls to ibm,configure-connector with the same entry from the “ibm,drc-indexes” or “ibm,drc-info” property will restart the configuration of devices which were not completely configured.' We can use this kernel behavior in our favor. If a DRC connector reconfiguration for a LMB that we marked as unplug pending happens, this indicates that the kernel changed its mind about the unplug and is reasserting that it will keep using all the LMBs of the DIMM. In this case, it's safe to assume that the whole DIMM device unplug was cancelled. This patch hops into rtas_ibm_configure_connector() and, in the scenario described above, clear the unplug state for the DIMM device. This will not solve all the problems we still have with memory unplug, but it will cover this case where the kernel reconfigures LMBs after a failed unplug. We are a bit more resilient, without using an unreliable timeout, and we didn't make the remaining error cases any worse. [1] arch/powerpc/platforms/pseries/hotplug-memory.c Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210222194531.62717-6-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * spapr_drc.c: add hotunplug timeout for CPUsDaniel Henrique Barboza2021-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a reliable way to make a CPU hotunplug fail in the pseries machine. Hotplug a CPU A, then offline all other CPUs inside the guest but A. When trying to hotunplug A the guest kernel will refuse to do it, because A is now the last online CPU of the guest. PAPR has no 'error callback' in this situation to report back to the platform, so the guest kernel will deny the unplug in silent and QEMU will never know what happened. The unplug pending state of A will remain until the guest is shutdown or rebooted. Previous attempts of fixing it (see [1] and [2]) were aimed at trying to mitigate the effects of the problem. In [1] we were trying to guess which guest CPUs were online to forbid hotunplug of the last online CPU in the QEMU layer, avoiding the scenario described above because QEMU is now failing in behalf of the guest. This is not robust because the last online CPU of the guest can change while we're in the middle of the unplug process, and our initial assumptions are now invalid. In [2] we were accepting that our unplug process is uncertain and the user should be allowed to spam the IRQ hotunplug queue of the guest in case the CPU hotunplug fails. This patch presents another alternative, using the timeout infrastructure introduced in the previous patch. CPU hotunplugs in the pSeries machine will now timeout after 15 seconds. This is a long time for a single CPU unplug to occur, regardless of guest load - although the user is *strongly* encouraged to *not* hotunplug devices from a guest under high load - and we can be sure that something went wrong if it takes longer than that for the guest to release the CPU (the same can't be said about memory hotunplug - more on that in the next patch). Timing out the unplug operation will reset the unplug state of the CPU and allow the user to try it again, regardless of the error situation that prevented the hotunplug to occur. Of all the not so pretty fixes/mitigations for CPU hotunplug errors in pSeries, timing out the operation is an admission that we have no control in the process, and must assume the worst case if the operation doesn't succeed in a sensible time frame. [1] https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg03353.html [2] https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg04400.html Reported-by: Xujun Ma <xuma@redhat.com> Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1911414 Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210222194531.62717-5-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * spapr_drc.c: introduce unplug_timeout_timerDaniel Henrique Barboza2021-03-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LoPAR spec provides no way for the guest kernel to report failure of hotplug/hotunplug events. This wouldn't be bad if those operations were granted to always succeed, but that's far for the reality. What ends up happening is that, in the case of a failed hotunplug, regardless of whether it was a QEMU error or a guest misbehavior, the pSeries machine is retaining the unplug state of the device in the running guest. This state is cleanup in machine reset, where it is assumed that this state represents a device that is pending unplug, and the device is hotunpluged from the board. Until the reset occurs, any hotunplug operation of the same device is forbid because there is a pending unplug state. This behavior has at least one undesirable side effect. A long standing pending unplug state is, more often than not, the result of a hotunplug error. The user had to dealt with it, since retrying to unplug the device is noy allowed, and then in the machine reset we're removing the device from the guest. This means that we're failing the user twice - failed to hotunplug when asked, then hotunplugged without notice. Solutions to this problem range between trying to predict when the hotunplug will fail and forbid the operation from the QEMU layer, from opening up the IRQ queue to allow for multiple hotunplug attempts, from telling the users to 'reboot the machine if something goes wrong'. The first solution is flawed because we can't fully predict guest behavior from QEMU, the second solution is a trial and error remediation that counts on a hope that the unplug will eventually succeed, and the third is ... well. This patch introduces a crude, but effective solution to hotunplug errors in the pSeries machine. For each unplug done, we'll timeout after some time. If a certain amount of time passes, we'll cleanup the hotunplug state from the machine. During the timeout period, any unplug operations in the same device will still be blocked. After that, we'll assume that the guest failed the operation, and allow the user to try again. If the timeout is too short we'll prevent legitimate hotunplug situations to occur, so we'll need to overestimate the regular time an unplug operation takes to succeed to account that. The true solution for the hotunplug errors in the pSeries machines is a PAPR change to allow for the guest to warn the platform about it. For now, the work done in this timeout design can be used for the new PAPR 'abort hcall' in the future, given that for both cases we'll need code to cleanup the existing unplug states of the DRCs. At this moment we're adding the basic wiring of the timer into the DRC. Next patch will use the timer to timeout failed CPU hotunplugs. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210222194531.62717-4-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * spapr: rename spapr_drc_detach() to spapr_drc_unplug_request()Daniel Henrique Barboza2021-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spapr_drc_detach() is not the best name for what the function does. The function does not detach the DRC, it makes an uncommited attempt to do it. It'll mark the DRC as pending unplug, via the 'unplug_request' flag, and only if the DRC state is drck->empty_state it will detach the DRC, via spapr_drc_release(). This is a contrast with its pair spapr_drc_attach(), where the function is indeed creating the DRC QOM object. If you know what spapr_drc_attach() does, you can be misled into thinking that spapr_drc_detach() is removing the DRC from QEMU internal state, which isn't true. The current role of this function is better described as a request for detach, since there's no guarantee that we're going to detach the DRC in the end. Rename the function to spapr_drc_unplug_request to reflect what is is doing. The initial idea was to change the name to spapr_drc_detach_request(), and later on change the unplug_request flag to detach_request. However, unplug_request is a migratable boolean for a long time now and renaming it is not worth the trouble. spapr_drc_unplug_request() setting drc->unplug_request is more natural than spapr_drc_detach_request setting drc->unplug_request. Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210222194531.62717-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | Merge remote-tracking branch ↵Peter Maydell2021-03-113-3/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging Pull request # gpg: Signature made Wed 10 Mar 2021 21:56:09 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.0-pull-request: (22 commits) sysemu: Let VMChangeStateHandler take boolean 'running' argument sysemu/runstate: Let runstate_is_running() return bool hw/lm32/Kconfig: Have MILKYMIST select LM32_DEVICES hw/lm32/Kconfig: Rename CONFIG_LM32 -> CONFIG_LM32_DEVICES hw/lm32/Kconfig: Introduce CONFIG_LM32_EVR for lm32-evr/uclinux boards qemu-common.h: Update copyright string to 2021 tests/fp/fp-test: Replace the word 'blacklist' qemu-options: Replace the word 'blacklist' seccomp: Replace the word 'blacklist' scripts/tracetool: Replace the word 'whitelist' ui: Replace the word 'whitelist' virtio-gpu: Adjust code space style exec/memory: Use struct Object typedef fuzz-test: remove unneccessary debugging flags net: Use id_generate() in the network subsystem, too MAINTAINERS: Fix the location of tools manuals vhost_user_gpu: Drop dead check for g_malloc() failure backends/dbus-vmstate: Fix short read error handling target/hexagon/gen_tcg_funcs: Fix a typo hw/elf_ops: Fix a typo ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | exec/memory: Use struct Object typedefPhilippe Mathieu-Daudé2021-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We forward-declare Object typedef in "qemu/typedefs.h" since commit ca27b5eb7cd ("qom/object: Move Object typedef to 'qemu/typedefs.h'"). Use it everywhere to make the code simpler. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210225182003.3629342-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | hw/elf_ops: Fix a typoPhilippe Mathieu-Daudé2021-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | g_mapped_file_new_from_fd()'s parameter is named 'writable'. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: David Edmondson <dme@dme.org> Message-Id: <20210225181344.3623720-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | Various spelling fixesMichael Tokarev2021-03-091-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | An assorted set of spelling fixes in various places. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210309111510.79495-1-mjt@msgid.tls.msk.ru> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge remote-tracking branch ↵Peter Maydell2021-03-115-148/+1Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/stsquad/tags/pull-testing-docs-xen-updates-100321-2' into staging Testing, guest-loader and other misc tweaks - add warning text to quickstart example - add CFI tests to CI - use --arch-only for docker pre-requisites - fix .editorconfig for emacs - add guest-loader for Xen-like hypervisor testing - move generic-loader docs into manual proper - move semihosting out of hw/ # gpg: Signature made Wed 10 Mar 2021 15:35:31 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-docs-xen-updates-100321-2: semihosting: Move hw/semihosting/ -> semihosting/ semihosting: Move include/hw/semihosting/ -> include/semihosting/ tests/avocado: add boot_xen tests docs: add some documentation for the guest-loader docs: move generic-loader documentation into the main manual hw/core: implement a guest-loader to support static hypervisor guests device_tree: add qemu_fdt_setprop_string_array helper hw/riscv: migrate fdt field to generic MachineState hw/board: promote fdt from ARM VirtMachineState to MachineState .editorconfig: update the automatic mode setting for Emacs tests/docker: Use --arch-only when building Debian cross image gitlab-ci.yml: Add jobs to test CFI flags gitlab-ci.yml: Allow custom # of parallel linkers tests/docker: add a test-tcg for building then running check-tcg docs/system: add a gentle prompt for the complexity to come Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-102-146/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to move the semihosting code out of hw/ in the next patch. This patch contains the mechanical steps, created using: $ git mv include/hw/semihosting/ include/ $ sed -i s,hw/semihosting,semihosting, $(git grep -l hw/semihosting) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210226131356.3964782-2-f4bug@amsat.org> Message-Id: <20210305135451.15427-2-alex.bennee@linaro.org>
| * | hw/riscv: migrate fdt field to generic MachineStateAlex Bennée2021-03-101-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a mechanical change to make the fdt available through MachineState. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210303173642.3805-3-alex.bennee@linaro.org>
| * | hw/board: promote fdt from ARM VirtMachineState to MachineStateAlex Bennée2021-03-102-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | The use of FDT's is quite common across our various platforms. To allow the guest loader to tweak it we need to make it available in the generic state. This creates the field and migrates the initial user to use the generic field. Other boards will be updated in later patches. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210303173642.3805-2-alex.bennee@linaro.org>
* | Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210309' ↵Peter Maydell2021-03-112-0/+50
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Aspeed patches : * New model for the Aspeed LPC controller * Misc cleanups # gpg: Signature made Tue 09 Mar 2021 11:54:25 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20210309: hw/misc: Model KCS devices in the Aspeed LPC controller hw/misc: Add a basic Aspeed LPC controller model hw/arm: ast2600: Correct the iBT interrupt ID hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC hw/arm/aspeed: Fix location of firmware images in documentation arm/ast2600: Fix SMP booting with -kernel Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/misc: Model KCS devices in the Aspeed LPC controllerAndrew Jeffery2021-03-092-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host. Expose support on the BMC side by implementing the usual MMIO behaviours, and expose the ability to inspect the KCS registers in "host" style by accessing QOM properties associated with each register. The model caters to the IRQ style of both the AST2600 and the earlier SoCs (AST2400 and AST2500). The AST2600 allocates an IRQ for each LPC sub-device, while there is a single IRQ shared across all subdevices on the AST2400 and AST2500. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210302014317.915120-6-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw/misc: Add a basic Aspeed LPC controller modelCédric Le Goater2021-03-092-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | | Merge remote-tracking branch ↵Peter Maydell2021-03-1014-35/+403
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20210310' into staging target-arm queue: * Add new mps3-an547 board * target/arm: Restrict v7A TCG cpus to TCG accel * Implement a Xilinx CSU DMA model * hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() # gpg: Signature made Wed 10 Mar 2021 13:56:20 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210310: (54 commits) hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_ hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips hw/ssi: xilinx_spips: Clean up coding convention issues hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI hw/arm: xlnx-zynqmp: Clean up coding convention issues hw/dma: Implement a Xilinx CSU DMA model target/arm: Restrict v7A TCG cpus to TCG accel tests/qtest/sse-timer-test: Test counter scaling changes tests/qtest/sse-timer-test: Test the system timer tests/qtest/sse-timer-test: Add simple test of the SSE counter docs/system/arm/mps2.rst: Document the new mps3-an547 board hw/arm/mps2-tz: Add new mps3-an547 board hw/arm/mps2-tz: Make initsvtor0 setting board-specific hw/arm/mps2-tz: Support running APB peripherals on different clock hw/misc/mps2-scc: Implement changes for AN547 hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate hw/arm/mps2-tz: Make UART overflow IRQ board-specific hw/arm/armsse: Add SSE-300 support ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spipsXuzhou Cheng2021-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the Xilinx CSU DMA model is implemented, the existing DMA related dead codes in the ZynqMP QSPI are useless and should be removed. The maximum register number is also updated to only include the QSPI registers. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPIXuzhou Cheng2021-03-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream link of GQSPI to CSU DMA. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210303135254.3970-4-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm: xlnx-zynqmp: Clean up coding convention issuesXuzhou Cheng2021-03-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some coding convention warnings in xlnx-zynqmp.c and xlnx-zynqmp.h, as reported by: $ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h $ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c Let's clean them up. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210303135254.3970-3-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/dma: Implement a Xilinx CSU DMA modelXuzhou Cheng2021-03-081-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ZynqMP QSPI supports SPI transfer using DMA mode, but currently this is unimplemented. When QSPI is programmed to use DMA mode, QEMU will crash. This is observed when testing VxWorks 7. This adds a Xilinx CSU DMA model and the implementation is based on https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c. The DST part of the model is verified along with ZynqMP GQSPI model. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210303135254.3970-2-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/misc/mps2-fpgaio: Support AN547 DBGCTRL registerPeter Maydell2021-03-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the AN547 image, the FPGAIO block has an extra DBGCTRL register, which is used to control the SPNIDEN, SPIDEN, NPIDEN and DBGEN inputs to the CPU. These signals control when the CPU permits use of the external debug interface. Our CPU models don't implement the external debug interface, so we model the register as reads-as-written. Implement the register, with a property defining whether it is present, and allow mps2-tz boards to specify that it is present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-39-peter.maydell@linaro.org
| * | hw/arm/armsse: Add SSE-300 supportPeter Maydell2021-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have sufficiently parameterised the code, we can add SSE-300 support by adding a new entry to the armsse_variants[] array. Note that the main watchdog (unlike the s32k watchdog) in the SSE-300 is a different device from the CMSDK watchdog; we don't have a model of it so we leave it as a TYPE_UNIMPLEMENTED_DEVICE stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-36-peter.maydell@linaro.org
| * | hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL blockPeter Maydell2021-03-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register block. Because this block is per-CPU and does not clash with any of the SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the existing has_cachectrl, has_cpusectrl and has_cpuid, rather than trying to add per-CPU-device support to the devinfo array handling code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-35-peter.maydell@linaro.org
| * | hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfoPeter Maydell2021-03-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-300 has four timers of type TYPE_SSE_TIMER; add support in the code for having these in an ARMSSEDeviceInfo array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-34-peter.maydell@linaro.org
| * | hw/arm/armsse: Add support for SSE variants with a system counterPeter Maydell2021-03-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-300 has a system counter device; add support for SSE variants having this device. As with the existing devices like the cache control block, CPUID block, etc, we don't try to make the MMIO addresses configurable. We can do that if and when we need to model a future SSE variant which has the counter in a different location. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-33-peter.maydell@linaro.org
| * | hw/arm/armsse: Add missing SSE-200 SYS_PPUPeter Maydell2021-03-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We forgot to implement a TYPE_UNIMPLEMENTED_DEVICE stub for the SYS_PPU in the SSE-200, which is at 0x50022000. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-31-peter.maydell@linaro.org
| * | hw/arm/armsse: Move PPUs into data-driven frameworkPeter Maydell2021-03-081-9/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the PPUs into the data-driven device placement framework. We don't implement them, so they are just TYPE_UNIMPLEMENTED stubs. Because the SSE-200 and the IotKit diverge here (the IoTKit does not have the PPUs) we need to separate out the ARMSSEDeviceInfo for the two variants, and only add the PPUs to the SSE-200. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-30-peter.maydell@linaro.org
| * | hw/arm/armsse: Move s32ktimer into data-driven frameworkPeter Maydell2021-03-081-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the CMSDK timer that uses the S32K slow clock into the data-driven device placement framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-27-peter.maydell@linaro.org
| * | hw/arm/armsse: Move watchdogs into data-driven frameworkPeter Maydell2021-03-081-3/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the CMSDK watchdog device handling into the data-driven device placement framework. This is slightly more complicated because these devices might wire their IRQs up to the NMI line, and because one of them uses the slow 32KHz clock rather than the main clock. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-26-peter.maydell@linaro.org
| * | hw/arm/armsse: Add framework for data-driven device placementPeter Maydell2021-03-081-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-300 is mostly the same as the SSE-200, but it has moved some of the devices in the memory map and uses different device types in some cases. To accommodate this, add a framework where the placement and wiring of some devices can be specified in a data table. This commit adds the framework for this data-driven device placement, and makes the CMSDK APB timer devices use it. Subsequent commits will convert the other devices which differ between SSE-200 and SSE-300. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-24-peter.maydell@linaro.org
| * | hw/arm/armsse: Add a define for number of IRQs used by the SSE itselfPeter Maydell2021-03-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE uses 32 interrupts for its own devices, and then passes through its expansion IRQ inputs to the CPU's interrupts 33 and upward. Add a define for the number of IRQs the SSE uses for itself, instead of hardcoding 32. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-23-peter.maydell@linaro.org
| * | hw/arm/armsse: Use an array for apb_ppc fields in the state structurePeter Maydell2021-03-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the apb_ppc0 and apb_ppc1 fields in the ARMSSE state struct to use an array instead of two separate fields. We already had one place in the code that wanted to be able to refer to the PPC by index, and we're about to add more code like that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-22-peter.maydell@linaro.org
| * | hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register blockPeter Maydell2021-03-081-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-300 has a new register block CPU<N>_PWRCTRL. There is one instance of this per CPU in the system (so just one for the SSE-300), and as well as the usual CIDR/PIDR ID registers it has just one register, CPUPWRCFG. This register allows the guest to configure behaviour of the system in power-down and deep-sleep states. Since QEMU does not model those, we make the register a dummy reads-as-written implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-21-peter.maydell@linaro.org
| * | hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registersPeter Maydell2021-03-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sysctl PDCM_PD_*_SENSE registers control various power domains in the system and allow the guest to configure which conditions keep a power domain awake and what power state to use when the domain is in a low power state. QEMU doesn't model power domains, so for us these registers are dummy reads-as-written implementations. The SSE-300 has a different power domain setup, so the set of registers is slightly different: Offset SSE-200 SSE-300 --------------------------------------------------- 0x200 PDCM_PD_SYS_SENSE PDCM_PD_SYS_SENSE 0x204 reserved PDCM_PD_CPU0_SENSE 0x208 reserved reserved 0x20c PDCM_PD_SRAM0_SENSE reserved 0x210 PDCM_PD_SRAM1_SENSE reserved 0x214 PDCM_PD_SRAM2_SENSE PDCM_PD_VMR0_SENSE 0x218 PDCM_PD_SRAM3_SENSE PDCM_PD_VMR1_SENSE Offsets 0x200 and 0x208 are the same for both, so handled in a previous commit; here we deal with 0x204, 0x20c, 0x210, 0x214, 0x218. (We can safely add new lines to the SSE300 vmstate because no board uses this device in an SSE300 yet.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-18-peter.maydell@linaro.org
| * | hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL registerPeter Maydell2021-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-300 has a new PWRCTRL register at offset 0x1fc (previously reserved). This register controls accessibility of some registers in the Power Policy Units (PPUs). Since QEMU doesn't implement the PPUs, we don't need to implement any real behaviour for this register, so we just handle the UNLOCK bit which controls whether writes to the register itself are permitted and otherwise make it be reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-17-peter.maydell@linaro.org
| * | hw/timer/sse-timer: Model the SSE Subsystem System TimerPeter Maydell2021-03-081-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-300 includes some timers which are a different kind to those in the SSE-200. Model them. These timers are documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-13-peter.maydell@linaro.org
| * | hw/timer/sse-counter: Model the SSE Subsystem System CounterPeter Maydell2021-03-081-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-300 includes a counter module; implement a model of it. This counter is documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-12-peter.maydell@linaro.org
| * | hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDRPeter Maydell2021-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SSE-300, the SYSINFO register block has two new registers: * SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3; since the SSE-300 can only be configured with a single CPU it is always zero * IIDR is the subsystem implementation identity register; its value is set by the SoC integrator, so we plumb this in from the armsse.c code as we do with SYS_VERSION and SYS_CONFIG Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-11-peter.maydell@linaro.org
| * | hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register valuesPeter Maydell2021-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The version of the SYSINFO Register Block in the SSE-300 has different CIDR/PIDR register values to the SSE-200; pass in the sse-version property and use it to select the correct ID register values. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-9-peter.maydell@linaro.org
| * | hw/misc/iotkit-secctl.c: Implement SSE-300 PID register valuesPeter Maydell2021-03-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The versions of the Secure Access Configuration Register Block and Non-secure Access Configuration Register Block in the SSE-300 are the same as those in the SSE-200, but the CIDR/PIDR ID register values are different. Plumb through the sse-version property and use it to select the correct ID register values. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-8-peter.maydell@linaro.org
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 15:01:24 +0100