summaryrefslogtreecommitdiffstats
path: root/include/hw
Commit message (Expand)AuthorAgeFilesLines
...
| * | sifive_u: Rename memmap enum constantsEduardo Habkost2020-09-181-17/+17
| * | sifive_e: Rename memmap enum constantsEduardo Habkost2020-09-181-19/+19
| |/
* / hw/i386/vmport: Drop superfluous parenthesis around function typedefPhilippe Mathieu-Daudé2020-09-181-1/+1
|/
* x86: move cpu hotplug from pc to x86Gerd Hoffmann2020-09-171-0/+10
* x86: move acpi_dev from pc/microvmGerd Hoffmann2020-09-173-2/+1Star
* x86: constify x86_machine_is_*_enabledGerd Hoffmann2020-09-171-2/+2
* microvm/acpi: add minimal acpi supportGerd Hoffmann2020-09-171-0/+9
* microvm: make virtio irq base runtime configurableGerd Hoffmann2020-09-171-1/+1
* acpi: move acpi_dsdt_add_power_button() to gedGerd Hoffmann2020-09-171-0/+1
* acpi: ged: add x86 device variant.Gerd Hoffmann2020-09-171-0/+4
* acpi: ged: add control regsGerd Hoffmann2020-09-171-0/+12
* virtio-gpu: make virtio_gpu_ops staticGerd Hoffmann2020-09-151-2/+1Star
* hw/arm/npcm7xx: add board setup stub for CPU and UART clocksHavard Skinnemoen2020-09-141-0/+1
* hw/ssi: NPCM7xx Flash Interface Unit device modelHavard Skinnemoen2020-09-142-0/+75
* hw/mem: Stubbed out NPCM7xx Memory Controller modelHavard Skinnemoen2020-09-142-0/+38
* hw/nvram: NPCM7xx OTP device modelHavard Skinnemoen2020-09-142-0/+82
* hw/arm: Add two NPCM7xx-based machinesHavard Skinnemoen2020-09-141-0/+19
* hw/arm: Add NPCM730 and NPCM750 SoC modelsHavard Skinnemoen2020-09-141-0/+85
* hw/timer: Add NPCM7xx Timer device modelHavard Skinnemoen2020-09-141-0/+78
* hw/misc: Add NPCM7xx Clock Controller device modelHavard Skinnemoen2020-09-141-0/+48
* hw/misc: Add NPCM7xx System Global Control Registers device modelHavard Skinnemoen2020-09-141-0/+43
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-1317-86/+319
|\
| * hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-101-0/+0
| * hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-101-0/+0
| * hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-101-0/+0
| * hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-81/+0Star
| * hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-0/+0
| * hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-103-2/+2
| * hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-102-1/+1
| * hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-102-1/+1
| * hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-101-0/+0
| * hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-101-0/+11
| * hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+3
| * hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+3
| * hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+7
| * hw/net: cadence_gem: Add a new 'phy-addr' propertyBin Meng2020-09-101-0/+2
| * hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-101-0/+11
| * hw/dma: Add SiFive platform DMA controller emulationBin Meng2020-09-101-0/+57
| * hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-101-0/+4
| * hw/sd: Add Cadence SDHCI emulationBin Meng2020-09-101-0/+47
| * hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-101-0/+20
| * hw/char: Add Microchip PolarFire SoC MMUART emulationBin Meng2020-09-101-0/+61
| * hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-101-0/+88
| * hw/riscv: hart: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+1
* | pc87312: Rename TYPE_PC87312_SUPERIO to TYPE_PC87312Eduardo Habkost2020-09-091-2/+2
* | sabre: Rename SABRE_DEVICE to SABREEduardo Habkost2020-09-091-1/+1
* | esp: Rename ESP_STATE to ESPEduardo Habkost2020-09-091-1/+1
* | ahci: Rename ICH_AHCI to ICH9_AHCIEduardo Habkost2020-09-091-1/+1
* | vmgenid: Rename VMGENID_DEVICE to TYPE_VMGENIDEduardo Habkost2020-09-091-3/+3
* | ap-device: Rename AP_DEVICE_TYPE to TYPE_AP_DEVICEEduardo Habkost2020-09-091-2/+2