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* hw/i386/pc: enable PVH only for machine type >= 4.0Stefano Garzarella2019-02-051-0/+3
| | | | | | | | | In order to avoid migration issues, we enable PVH only for machine type >= 4.0 Suggested-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* pvh: Boot uncompressed kernel using direct boot ABILiam Merwick2019-02-051-0/+10
| | | | | | | | | | | | | | | | | | | | These changes (along with corresponding Linux kernel and qboot changes) enable a guest to be booted using the x86/HVM direct boot ABI. This commit adds a load_elfboot() routine to pass the size and location of the kernel entry point to qboot (which will fill in the start_info struct information needed to to boot the guest). Having loaded the ELF binary, load_linux() will run qboot which continues the boot. The address for the kernel entry point is read from an ELF Note in the uncompressed kernel binary by a helper routine passed to load_elf(). Co-developed-by: George Kennedy <George.Kennedy@oracle.com> Signed-off-by: George Kennedy <George.Kennedy@oracle.com> Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* pvh: Add x86/HVM direct boot ABI header fileLiam Merwick2019-02-051-0/+146
| | | | | | | | | | | | | | | | | The x86/HVM direct boot ABI permits Qemu to be able to boot directly into the uncompressed Linux kernel binary with minimal firmware involvement. https://xenbits.xen.org/docs/unstable/misc/pvh.html This commit adds the header file that defines the start_info struct that needs to be populated in order to use this ABI. The canonical version of start_info.h is in the Xen codebase. (like QEMU, the Linux kernel uses a copy as well). Signed-off-by: Liam Merwick <Liam.Merwick@oracle.com> Reviewed-by: Konrad Rzeszutek Wilk <Konrad.Wilk@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* elf-ops.h: Add get_elf_note_type()Liam Merwick2019-02-051-0/+75
| | | | | | | | | | | | | | Introduce a routine which, given a pointer to a range of ELF Notes, searches through them looking for a note matching the type specified and returns a pointer to the matching ELF note. get_elf_note_type() is used by elf_load[32|64]() to find the specified note type required by the 'elf_note_fn' parameter added in the previous commit. Signed-off-by: Liam Merwick <Liam.Merwick@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Liam Merwick <liam.merwick@oracle.com>
* elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick2019-02-052-1/+10
| | | | | | | | | | | | | | | | | | | This patch adds an optional function pointer, 'elf_note_fn', to load_elf() which causes load_elf() to additionally parse any ELF program headers of type PT_NOTE and check to see if the ELF Note is of the type specified by the 'translate_opaque' arg. If a matching ELF Note is found then the specfied function pointer is called to process the ELF note. Passing a NULL function pointer results in ELF Notes being skipped. The first consumer of this functionality is the PVHboot support which needs to read the XEN_ELFNOTE_PHYS32_ENTRY ELF Note while loading the uncompressed kernel binary in order to discover the boot entry address for the x86/HVM direct boot ABI. Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-02-04' into ↵Peter Maydell2019-02-051-2/+30
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging nbd patches for 2019-02-04 - deprecate 'qemu-nbd --partition' - preparation for NBD reconnect, including better logging of read errors # gpg: Signature made Tue 05 Feb 2019 03:50:56 GMT # gpg: using RSA key A7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full] # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full] # gpg: aka "[jpeg image of size 6874]" [full] # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2019-02-04: block/nbd-client: rename read_reply_co to connection_co block/nbd-client: don't check ioc block/nbd-client: fix nbd_reply_chunk_iter_receive block/nbd-client: split connection from initialization block/nbd: move connection code from block/nbd to block/nbd-client block/nbd-client: split channel errors from export errors nbd: generalize usage of nbd_read qemu-nbd: Deprecate qemu-nbd --partition Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * nbd: generalize usage of nbd_readVladimir Sementsov-Ogievskiy2019-02-041-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We generally do very similar things around nbd_read: error_prepend specifying what we have tried to read, and be_to_cpu conversion of integers. So, it seems reasonable to move common things to helper functions, which: 1. simplify code a bit 2. generalize nbd_read error descriptions, all starting with "Failed to read" 3. make it more difficult to forget to convert things from BE Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20190128165830.165170-1-vsementsov@virtuozzo.com> [eblake: rename macro to DEF_NBD_READ_N and formatting tweaks; checkpatch has false positive complaint] Signed-off-by: Eric Blake <eblake@redhat.com>
* | Merge remote-tracking branch 'remotes/xtensa/tags/20190204-xtensa' into stagingPeter Maydell2019-02-051-0/+44
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | target/xtensa: SMP updates and various fixes - fix CPU wakeup on runstall changes; expose runstall as an IRQ line; - place mini-bootloader at the BSP reset vector; - expose CPU core frequency in XTFPGA board FPGA register; - rearrange access to external interrupts of xtensa cores; - add MX interrupt distributor and use it on SMP XTFPGA boards; - add test_mmuhifi_c3 xtensa core variant; - raise number of CPUs that can be instantiated on XTFPGA boards. # gpg: Signature made Mon 04 Feb 2019 18:59:32 GMT # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190204-xtensa: hw/xtensa: xtfpga: raise CPU number limit target/xtensa: add test_mmuhifi_c3 core hw/xtensa: xtfpga: use MX PIC for SMP target/xtensa: add MX interrupt controller target/xtensa: expose core runstall as an IRQ line target/xtensa: rearrange access to external interrupts target/xtensa: drop function xtensa_timer_irq target/xtensa: fix access to the INTERRUPT SR hw/xtensa: xtfpga: use core frequency hw/xtensa: xtfpga: fix bootloader placement in SMP target/xtensa: add qemu_cpu_kick to xtensa_runstall Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/xtensa: add MX interrupt controllerMax Filippov2019-01-281-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MX interrupt controller is a collection of the following devices accessible through the external registers interface: - interrupt distributor can route each external IRQ line to the corresponding external IRQ pin of selected subset of connected xtensa cores. It has per-CPU and per-IRQ enable signals and per-IRQ software assert signals; - IPI controller has 16 per-CPU IPI signals that may be routed to a combination of 3 designated external IRQ pins of connected xtensa cores; - cache coherecy register controls core L1 cache participation in the SMP cluster cache coherency protocol; - runstall register lets BSP core stall and unstall AP cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* | mmap-alloc: fix hugetlbfs misaligned length in ppc64Murilo Opsfelder Araujo2019-02-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 7197fb4058bcb68986bae2bb2c04d6370f3e7218 ("util/mmap-alloc: fix hugetlb support on ppc64") fixed Huge TLB mappings on ppc64. However, we still need to consider the underlying huge page size during munmap() because it requires that both address and length be a multiple of the underlying huge page size for Huge TLB mappings. Quote from "Huge page (Huge TLB) mappings" paragraph under NOTES section of the munmap(2) manual: "For munmap(), addr and length must both be a multiple of the underlying huge page size." On ppc64, the munmap() in qemu_ram_munmap() does not work for Huge TLB mappings because the mapped segment can be aligned with the underlying huge page size, not aligned with the native system page size, as returned by getpagesize(). This has the side effect of not releasing huge pages back to the pool after a hugetlbfs file-backed memory device is hot-unplugged. This patch fixes the situation in qemu_ram_mmap() and qemu_ram_munmap() by considering the underlying page size on ppc64. After this patch, memory hot-unplug releases huge pages back to the pool. Fixes: 7197fb4058bcb68986bae2bb2c04d6370f3e7218 Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | spapr: move the interrupt presenters under machine_dataCédric Le Goater2019-02-041-0/+2
| | | | | | | | | | | | | | | | Next step is to remove them from under the PowerPCCPU Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | ppc/pnv: introduce a CPU machine_dataCédric Le Goater2019-02-041-0/+9
| | | | | | | | | | | | | | | | | | Include the interrupt presenter under the machine_data as we plan to remove it from under PowerPCCPU Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | xive: add a get_tctx() method to the XiveRouterCédric Le Goater2019-02-041-28/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It provides a mean to retrieve the XiveTCTX of a CPU. This will become necessary with future changes which move the interrupt presenter object pointers under the PowerPCCPU machine_data. The PowerNV machine has an extra requirement on TIMA accesses that this new method addresses. The machine can perform indirect loads and stores on the TIMA on behalf of another CPU. The PIR being defined in the controller registers, we need a way to peek in the controller model to find the PIR value. The XiveTCTX is moved above the XiveRouter definition to avoid forward typedef declarations. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | ppc/xive: fix remaining XiveFabric namesCédric Le Goater2019-02-041-1/+1
| | | | | | | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | ppc4xx: Use ram_addr_t in ppc4xx_sdram_adjust()BALATON Zoltan2019-02-041-1/+1
| | | | | | | | | | | | | | | | To avoid overflow if larger values are added later use ram_addr_t for the sdram_bank_sizes parameter to match ram_size to which it is compared. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | smbus: Add a helper to generate SPD EEPROM dataBALATON Zoltan2019-02-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | There are several boards with SPD EEPROMs that are now using duplicated or slightly different hard coded data. Add a helper to generate SPD data for a memory module of given type and size that could be used by these boards (either as is or with further changes if needed) which should help cleaning this up and avoid further duplication. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell2019-02-013-77/+3Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block layer patches: - vmdk: Support for blockdev-create - block: Apply auto-read-only for ro-whitelist drivers - virtio-scsi: Fixes related to attaching/detaching iothreads - scsi-disk: Fixed erroneously detected multipath setup with multiple disks created with node-names. Added device_id property. - block: Fix hangs in synchronous APIs with iothreads - block: Fix invalidate_cache error path for parent activation - block-backend, mirror, qcow2, vpc, vdi, qemu-iotests: Minor fixes and code improvements # gpg: Signature made Fri 01 Feb 2019 15:23:10 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (27 commits) scsi-disk: Add device_id property scsi-disk: Don't use empty string as device id qtest.py: Wait for the result of qtest commands block: Fix invalidate_cache error path for parent activation iotests/236: fix transaction kwarg order iotests: Filter second BLOCK_JOB_ERROR from 229 virtio-scsi: Forbid devices with different iothreads sharing a blockdev scsi-disk: Acquire the AioContext in scsi_*_realize() virtio-scsi: Move BlockBackend back to the main AioContext on unplug block: Eliminate the S_1KiB, S_2KiB, ... macros block: Remove blk_attach_dev_legacy() / legacy_dev code block: Apply auto-read-only for ro-whitelist drivers uuid: Make qemu_uuid_bswap() take and return a QemuUUID block/vdi: Don't take address of fields in packed structs block/vpc: Don't take address of fields in packed structs vmdk: Reject excess extents in blockdev-create iotests: Add VMDK tests for blockdev-create iotests: Filter cid numbers in VMDK extent info vmdk: Implement .bdrv_co_create callback vmdk: Refactor vmdk_create_extent ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | block: Eliminate the S_1KiB, S_2KiB, ... macrosMarkus Armbruster2019-02-011-73/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We define 54 macros for the powers of two >= 1024. We use six, in six macro definitions. Four of them could just as well use the common MiB macro, so do that. The remaining two can't, because they get passed to stringify. Replace the macro by the literal number there. Slightly harder to read in one instance (1048576 vs. S_1MiB), so add a comment there. The other instance is a wash: 65536 vs S_64KiB. 65536 has been good enough for more than seven years there. This effectively reverts commit 540b8492618 and 1240ac558d3. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | block: Remove blk_attach_dev_legacy() / legacy_dev codeThomas Huth2019-02-011-3/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last user of blk_attach_dev_legacy() was the code in xen_disk which has recently been reworked. Now there is no user for this legacy function anymore. Thus we can finally remove all code related to the "legacy_dev" flag, too, and turn the related "void *" in block-backend.c into proper "DeviceState *" to fix some of the remaining TODOs there. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | uuid: Make qemu_uuid_bswap() take and return a QemuUUIDPeter Maydell2019-02-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently qemu_uuid_bswap() takes a pointer to the QemuUUID to be byte-swapped. This means it can't be used when the UUID to be swapped is in a packed member of a struct. It's also out of line with the general bswap*() functions we provide in bswap.h, which take the value to be swapped and return it. Make qemu_uuid_bswap() take a QemuUUID and return the swapped version. This fixes some clang warnings about taking the address of a packed struct member in block/vdi.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* | | Merge remote-tracking branch ↵Peter Maydell2019-02-018-20/+229
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20190201' into staging target-arm queue: * New machine mps2-an521 -- this is a model of the AN521 FPGA image for the MPS2 devboard * Fix various places where we failed to UNDEF invalid A64 instructions * Don't UNDEF a valid FCMLA on 32-bit inputs * Fix some bugs in the newly-added PAuth implementation * microbit: Implement NVMC non-volatile memory controller # gpg: Signature made Fri 01 Feb 2019 16:06:03 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190201: (47 commits) tests/microbit-test: Add tests for nRF51 NVMC arm: Instantiate NRF51 special NVM's and NVMC hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories target/arm: fix decoding of B{,L}RA{A,B} target/arm: fix AArch64 virtual address space size linux-user: Initialize aarch64 pac keys aarch64-linux-user: Enable HWCAP bits for PAuth aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1 target/arm: Always enable pac keys for user-only arm: Clarify the logic of set_pc() target/arm: Enable API, APK bits in SCR, HCR target/arm: Add a timer to predict PMU counter overflow target/arm: Send interrupts on PMU counter overflow target/arm/translate-a64: Fix mishandling of size in FCMLA decode target/arm/translate-a64: Fix FCMLA decoding error exec.c: Don't reallocate IOMMUNotifiers that are in use target/arm/translate-a64: Don't underdecode SDOT and UDOT target/arm/translate-a64: Don't underdecode FP insns target/arm/translate-a64: Don't underdecode add/sub extended register target/arm/translate-a64: Don't underdecode SIMD ld/st single ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | arm: Instantiate NRF51 special NVM's and NVMCSteffen Görtz2019-02-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190201023357.22596-3-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/nvram/nrf51_nvm: Add nRF51 non-volatile memoriesSteffen Görtz2019-02-011-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nRF51 contains three regions of non-volatile memory (NVM): - CODE (R/W): contains code - FICR (R): Factory information like code size, chip id etc. - UICR (R/W): Changeable configuration data. Lock bits, Code protection configuration, Bootloader address, Nordic SoftRadio configuration, Firmware configuration. Read and write access to the memories is managed by the Non-volatile memory controller. Memory schema: [ CPU ] -+- [ NVM, either FICR, UICR or CODE ] | | \- [ NVMC ] Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Tested-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190201023357.22596-2-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | arm: Clarify the logic of set_pc()Julia Suvorova2019-02-011-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the set_pc logic was unclear, which raised questions about whether it should be used directly, applying a value to PC or adding additional checks, for example, set the Thumb bit in Arm cpu. Let's set the set_pc logic for “Configure the PC, as was done in the ELF file” and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec. Signed-off-by: Julia Suvorova <jusual@mail.ru> Acked-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190129121817.7109-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/arm/armsse: Add SSE-200 modelPeter Maydell2019-02-011-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a model of the SSE-200, now we have put in all the code that lets us make it different from the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-22-peter.maydell@linaro.org
| * | | hw/arm/armsse: Add CPU_IDENTITY block to SSE-200Peter Maydell2019-02-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-21-peter.maydell@linaro.org
| * | | hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register blockPeter Maydell2019-02-011-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
| * | | hw/arm/armsse: Add unimplemented-device stub for CPU local control registersPeter Maydell2019-02-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-19-peter.maydell@linaro.org
| * | | hw/arm/armsse: Add unimplemented-device stub for cache control registersPeter Maydell2019-02-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-200 gives each CPU a register bank to use to control its L1 instruction cache. Put in an unimplemented-device stub for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
| * | | hw/arm/armsse: Add unimplemented-device stubs for PPUsPeter Maydell2019-02-011-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add unimplemented-device stubs for the various Power Policy Unit devices that the SSE-200 has. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-17-peter.maydell@linaro.org
| * | | hw/arm/armsse: Add unimplemented-device stubs for MHUsPeter Maydell2019-02-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-200 has two Message Handling Units (MHUs), which sit behind the APB PPC0. Wire up some unimplemented-device stubs for these, since we don't yet implement a real model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-16-peter.maydell@linaro.org
| * | | iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurablePeter Maydell2019-02-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SYS_VERSION and SYS_CONFIG register values differ between the IoTKit and SSE-200. Make them configurable via QOM properties rather than hard-coded, and set them appropriately in the ARMSSE code that instantiates the IOTKIT_SYSINFO device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-15-peter.maydell@linaro.org
| * | | hw/arm/armsse: Put each CPU in its own cluster objectPeter Maydell2019-02-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-14-peter.maydell@linaro.org
| * | | hw/arm/armsse: Give each CPU its own view of memoryPeter Maydell2019-02-011-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Give each CPU its own container memory region. This is necessary for two reasons: * some devices are instantiated one per CPU and the CPU sees only its own device * since a memory region can only be put into one container, we must give each armv7m object a different MemoryRegion as its 'memory' property, or a dual-CPU configuration will assert on realize when the second armv7m object tries to put the MR into a container when it is already in the first armv7m object's container Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-13-peter.maydell@linaro.org
| * | | hw/arm/armsse: Support dual-CPU configurationPeter Maydell2019-02-011-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-200 has two Cortex-M33 CPUs. These see the same view of memory, with the exception of the "private CPU region" which has per-CPU devices. Internal device interrupts for SSE-200 devices are mostly wired up to both CPUs, with the exception of a few per-CPU devices. External GPIO inputs on the SSE-200 device are provided for the second CPU's interrupts above 32, as is already the case for the first CPU. Refactor the code to support creation of multiple CPUs. For the moment we leave all CPUs with the same view of memory: this will not work in the multiple-CPU case, but we will fix this in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-12-peter.maydell@linaro.org
| * | | hw/arm/armsse: Make SRAM bank size configurablePeter Maydell2019-02-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-11-peter.maydell@linaro.org
| * | | hw/arm/armsse: Make number of SRAM banks parameterisedPeter Maydell2019-02-011-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-200 has four banks of SRAM, each with its own Memory Protection Controller, where the IoTKit has only one. Make the number of SRAM banks a field in ARMSSEInfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-10-peter.maydell@linaro.org
| * | | hw/misc/iotkit-secctl: Support 4 internal MPCsPeter Maydell2019-02-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSE-200 has 4 banks of SRAM, each with its own internal Memory Protection Controller. The interrupt status for these extra MPCs appears in the same security controller SECMPCINTSTATUS register as the MPC for the IoTKit's single SRAM bank. Enhance the iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE variant in use does not have all 4 MPCs then the unused inputs will simply result in the SECMPCINTSTATUS bits being zero as required.) The hardcoded constant "1"s in armsse.c indicate the actual number of SRAM MPCs the IoTKit has, and will be replaced in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-9-peter.maydell@linaro.org
| * | | hw/arm/iotkit: Rename files to hw/arm/armsse.[ch]Peter Maydell2019-02-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the files that used to be iotkit.[ch] to armsse.[ch] to reflect the fact they new cover multiple Arm subsystems for embedded. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-8-peter.maydell@linaro.org
| * | | hw/arm/iotkit: Refactor into abstract base class and subclassPeter Maydell2019-02-011-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arm SSE-200 Subsystem for Embedded is a revised and extended version of the older IoTKit SoC. Prepare for adding a model of it by refactoring the IoTKit code into an abstract base class which contains the functionality, driven by a class data block specific to each subclass. (This is the same approach used by the existing bcm283x SoC family implementation.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-6-peter.maydell@linaro.org
| * | | hw/arm/iotkit: Rename IoTKit to ARMSSEPeter Maydell2019-02-011-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arm IoTKit was effectively the forerunner of a series of subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200: https://developer.arm.com/products/system-design/subsystems These are generally quite similar, though later iterations have extra devices that earlier ones do not. We want to add a model of the SSE-200, which means refactoring the IoTKit code into an abstract base class and subclasses (using the same design that the bcm283x SoC and Aspeed SoC family implementations do). As a first step, rename the IoTKit struct and QOM macros to ARMSSE, which is what we're going to name the base class. We temporarily retain TYPE_IOTKIT to avoid changing the code that instantiates a TYPE_IOTKIT device here and then changing it back again when it is re-introduced as a subclass. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-5-peter.maydell@linaro.org
| * | | armv7m: Pass through start-powered-off CPU propertyPeter Maydell2019-02-011-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose "start-powered-off" as a property of the ARMv7M container, which we just pass through to the CPU object in the same way that we do for "init-svtor" and "idau". (We want this for the SSE-200, which powers up only the first CPU at reset and leaves the second powered down.) As with the other CPU properties here, we can't just use alias properties, because the CPU QOM object is not created until armv7m realize time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-4-peter.maydell@linaro.org
* | | Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190201-pull-request' ↵Peter Maydell2019-02-011-0/+41
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ui: fix build with SDL disabled, drop SDL1 support. # gpg: Signature made Fri 01 Feb 2019 12:30:47 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20190201-pull-request: ui: remove support for SDL1.2 in favour of SDL2 hw/display/milkymist-tmu2: Move inlined code from header to source hw/display/milkymist-tmu2: Explicit the dependency to both X11 / OpenGL configure: LM32 Milkymist Texture Mapping Unit (tmu2) also depends of X11 hw/display: Move Milkymist specific hardware out of common-obj list Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/display/milkymist-tmu2: Move inlined code from header to sourcePhilippe Mathieu-Daudé2019-02-011-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the complexity of milkymist_tmu2_create() into the source file. Doing so we avoid to include the X11/OpenGL headers in all LM32 devices, and we also avoid the duplicate declaration of glx_fbconfig_attr[] (it is already declared in hw/display/milkymist-tmu2.c). Since TYPE_MILKYMIST_TMU2 is now accessible, use it. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190130120005.23123-5-philmd@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | | Merge remote-tracking branch 'remotes/xanclic/tags/pull-block-2019-01-31' ↵Peter Maydell2019-01-313-0/+19
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Block patches: - New debugging QMP command to explore block graphs - Converted DPRINTF()s to trace events - Fixed qemu-io's use of getopt() for systems with optreset - Minor NVMe emulation fixes - An iotest fix # gpg: Signature made Thu 31 Jan 2019 00:51:46 GMT # gpg: using RSA key F407DB0061D5CF40 # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/xanclic/tags/pull-block-2019-01-31: iotests: Allow 147 to be run concurrently iotests: Bind qemu-nbd to localhost in 147 iotests.py: Add qemu_nbd_pipe() nvme: use pci_dev directly in nvme_realize nvme: ensure the num_queues is not zero nvme: use TYPE_NVME instead of constant string qemu-io: Add generic function for reinitializing optind. block/sheepdog: Convert from DPRINTF() macro to trace events block/file-posix: Convert from DPRINTF() macro to trace events block/curl: Convert from DPRINTF() macro to trace events block/ssh: Convert from DPRINTF() macro to trace events scripts: add render_block_graph function for QEMUMachine qapi: add x-debug-query-block-graph Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | qemu-io: Add generic function for reinitializing optind.Richard W.M. Jones2019-01-311-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On FreeBSD 11.2: $ nbdkit memory size=1M --run './qemu-io -f raw -c "aio_write 0 512" $nbd' Parsing error: non-numeric argument, or extraneous/unrecognized suffix -- aio_write After main option parsing, we reinitialize optind so we can parse each command. However reinitializing optind to 0 does not work on FreeBSD. What happens when you do this is optind remains 0 after the option parsing loop, and the result is we try to parse argv[optind] == argv[0] == "aio_write" as if it was the first parameter. The FreeBSD manual page says: In order to use getopt() to evaluate multiple sets of arguments, or to evaluate a single set of arguments multiple times, the variable optreset must be set to 1 before the second and each additional set of calls to getopt(), and the variable optind must be reinitialized. (From the rest of the man page it is clear that optind must be reinitialized to 1). The glibc man page says: A program that scans multiple argument vectors, or rescans the same vector more than once, and wants to make use of GNU extensions such as '+' and '-' at the start of optstring, or changes the value of POSIXLY_CORRECT between scans, must reinitialize getopt() by resetting optind to 0, rather than the traditional value of 1. (Resetting to 0 forces the invocation of an internal initialization routine that rechecks POSIXLY_CORRECT and checks for GNU extensions in optstring.) This commit introduces an OS-portability function called qemu_reset_optind which provides a way of resetting optind that works on FreeBSD and platforms that use optreset, while keeping it the same as now on other platforms. Note that the qemu codebase sets optind in many other places, but in those other places it's setting a local variable and not using getopt. This change is only needed in places where we are using getopt and the associated global variable optind. Signed-off-by: Richard W.M. Jones <rjones@redhat.com> Message-id: 20190118101114.11759-2-rjones@redhat.com Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
| * | qapi: add x-debug-query-block-graphVladimir Sementsov-Ogievskiy2019-01-312-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add a new command, returning block nodes (and their users) graph. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-id: 20181221170909.25584-2-vsementsov@virtuozzo.com Signed-off-by: Max Reitz <mreitz@redhat.com>
* | | Don't talk about the LGPL if the file is licensed under the GPLThomas Huth2019-01-304-16/+14Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some files claim that the code is licensed under the GPL, but then suddenly suggest that the user should have a look at the LGPL. That's of course non-sense, replace it with the correct GPL wording instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1548255083-8190-1-git-send-email-thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | | typo: apci->acpiDr. David Alan Gilbert2019-01-301-1/+1
|/ / | | | | | | | | | | | | | | | | | | apci_1_compatible should be acpi_1_compatible. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190125094047.22276-1-dgilbert@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | accel/tcg: Add cluster number to TCG TB hashPeter Maydell2019-01-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include the cluster number in the hash we use to look up TBs. This is important because a TB that is valid for one cluster at a given physical address and set of CPU flags is not necessarily valid for another: the two clusters may have different views of physical memory, or may have different CPU features (eg FPU present or absent). We put the cluster number in the high 8 bits of the TB cflags. This gives us up to 256 clusters, which should be enough for anybody. If we ever need more, or need more bits in cflags for other purposes, we could make tb_hash_func() take more data (and expand qemu_xxhash7() to qemu_xxhash8()). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20190121152218.9592-4-peter.maydell@linaro.org
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